SLVSB56C May   2012  – February 2014 TPS54160 , TPS54160A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation Output Current
      3. 8.3.3  Pulse Skip Eco-mode
      4. 8.3.4  Bootstrap Voltage (BOOT)
      5. 8.3.5  Low Dropout Operation
      6. 8.3.6  Error Amplifier
      7. 8.3.7  Voltage Reference
      8. 8.3.8  Adjusting the Output Voltage
      9. 8.3.9  Enable and Adjusting Undervoltage Lockout
      10. 8.3.10 Slow Start and Tracking Pin (SS/TR)
      11. 8.3.11 Overload Recovery Circuit
      12. 8.3.12 Sequencing
      13. 8.3.13 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      14. 8.3.14 Overcurrent Protection and Frequency Shift
      15. 8.3.15 Selecting the Switching Frequency
      16. 8.3.16 How to Interface to RT/CLK Pin
      17. 8.3.17 Power Good (PWRGD Pin)
      18. 8.3.18 Overvoltage Transient Protection
      19. 8.3.19 Thermal Shutdown
      20. 8.3.20 Small Signal Model for Loop Response
      21. 8.3.21 Simple Small Signal Model for Peak Current Mode Control
      22. 8.3.22 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VIN < 3.5 V (Minimum VIN)
      2. 8.4.2 Operation with EN Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1  Selecting the Switching Frequency
        2. 9.2.2.2  Output Inductor Selection (LO)
        3. 9.2.2.3  Output Capacitor
        4. 9.2.2.4  Catch Diode
        5. 9.2.2.5  Input Capacitor
        6. 9.2.2.6  Slow Start Capacitor
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Under Voltage Lock Out Set Point
        9. 9.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 9.2.2.10 Compensation
        11. 9.2.2.11 Power Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance.

  • To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
  • Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode.
  • The GND pin should be tied directly to the power pad under the device and the power pad.
  • The power pad should be connected to any internal PCB ground planes using multiple vias directly under the device.
  • The PH pin should be routed to the cathode of the catch diode and to the output inductor.
  • Since the PH connection is the switching node, the catch diode and output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
  • For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
  • The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the device and routed with minimal lengths of trace.
  • The additional external components can be placed approximately as shown.
  • It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.

11.2 Layout Example

layout_lvs795.gifFigure 65. PCB Layout Example