SLVSBK0D October   2012  – March 2017 TPS54340

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Load Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode
      4. 7.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Internal Soft-Start
      9. 7.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK) Terminal)
      10. 7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
      11. 7.3.11 Synchronization to RT/CLKTerminal
      12. 7.3.12 Overvoltage Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Small Signal Model for Loop Response
      15. 7.3.15 Simple Small Signal Model for Peak Current Mode Control
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VIN < 4.5 V (Minimum VIN)
      2. 7.4.2 Operation with EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedures
          1. 8.2.1.2.1  Custom Design with WEBENCH Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency
          3. 8.2.1.2.3  Output Inductor Selection (LO)
          4. 8.2.1.2.4  Output Capacitor
          5. 8.2.1.2.5  Catch Diode
          6. 8.2.1.2.6  Input Capacitor
          7. 8.2.1.2.7  Bootstrap Capacitor Selection
          8. 8.2.1.2.8  Undervoltage Lockout Set Point
          9. 8.2.1.2.9  Output Voltage and Feedback Resistors Selection
          10. 8.2.1.2.10 Minimum VIN
          11. 8.2.1.2.11 Compensation
          12. 8.2.1.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
          13. 8.2.1.2.13 Power Dissipation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Inverting Power
      3. 8.2.3 Split Rail Power Supply
    3. 8.3 WEBENCH Power Designer
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Estimated Circuit Area
  11. 11Device and Documentation Support
    1. 11.1 Custom Design with WEBENCH Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Receiving Notification of Documentation Updates
      2. 11.2.2 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Community Resources
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2.13 Power Dissipation

The following formulas show how to estimate the TPS54340 power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is operating in discontinuous conduction mode (DCM).

The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and supply current (PQ). Example calculations are shown with the 12 V typical input voltage of the design example.

Equation 52. TPS54340 q_pcond_lvsBK0.gif

spacer

Equation 53. TPS54340 q_psw_lvsb44.gif

spacer

Equation 54. TPS54340 q_pgd_lvsb44.gif

spacer

Equation 55. TPS54340 q_pq_lvsb44.gif

Where:

    IOUTis the output current (A).
    RDS(on) is the on-resistance of the high-side MOSFET (Ω).
    VOUT is the output voltage (V).
    VINis the input voltage (V).
    ƒswis the switching frequency (Hz).
    triseis the SW terminal voltage rise time and can be estimated by trise = VIN x 0.16ns/V + 3.0ns.
    QGis the total gate charge of the internal MOSFET.
    IQis the operating nonswitching supply current.

Therefore,

Equation 56. TPS54340 q_ptot_lvsBK0.gif

For given TA,

Equation 57. TPS54340 q_tj_lvs795.gif

For given TJMAX = 150°C

Equation 58. TPS54340 q_tamax_lvs795.gif

Where:

    Ptotis the total device power dissipation (W),
    TAis the ambient temperature (°C).
    TJis the junction temperature (°C).
    RTHis the thermal resistance of the package (°C/W).
    TJMAXis maximum junction temperature (°C)
    TAMAXis maximum ambient temperature (°C).

There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and PCB trace resistance impacting the overall efficiency of the regulator.