SLUSB69B May   2014  – July 2016 TPS544B20 , TPS544C20


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Turn-On and Turn-Off Delay and Sequencing
      2. 8.3.2  Pre-Biased Output Start-Up
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Differential Remote Sense and Output Voltage Setting
      5. 8.3.5  PMBus Output Voltage Adjustment
      6. 8.3.6  Switching Frequency
      7. 8.3.7  Soft-Start
      8. 8.3.8  Linear Regulators BP3 and BP6
      9. 8.3.9  External Bypass (BPEXT)
      10. 8.3.10 Current Monitoring and Low-Side MOSFET Overcurrent Protection
      11. 8.3.11 High-Side MOSFET Short-Circuit Protection
      12. 8.3.12 Over-Temperature Protection
      13. 8.3.13 Input Undervoltage Lockout (UVLO)
      14. 8.3.14 Output Overvoltage and Undervoltage Protection
      15. 8.3.15 Fault Protection Responses
      16. 8.3.16 PMBus General Description
      17. 8.3.17 PMBus Address
      18. 8.3.18 PMBus Connections
      19. 8.3.19 Auto ARA (Alert Response Address) Response
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode
      2. 8.4.2 Operation with Internal BP6 Regulator
      3. 8.4.3 Operation with BP External
      4. 8.4.4 Operation with CNTL Signal Control
      5. 8.4.5 Operation with OPERATION Control
      6. 8.4.6 Operation with CNTL and OPERATION Control
      7. 8.4.7 Operation with Output Margining
    5. 8.5 Programming
      1. 8.5.1 Supported PMBus Commands
    6. 8.6 Register Maps
      1. 8.6.1  OPERATION (01h)
        1. On
        2. Margin
      2. 8.6.2  ON_OFF_CONFIG (02h)
        1. pu
        2. cmd
        3. cpr
        4. pol
        5. cpa
      3. 8.6.3  CLEAR_FAULTS (03h)
      4. 8.6.4  WRITE_PROTECT (10h)
        1. bit5
        2. bit6
        3. bit7
      5. 8.6.5  STORE_USER_ALL (15h)
      6. 8.6.6  RESTORE_USER_ALL (16h)
      7. 8.6.7  CAPABILITY (19h)
      8. 8.6.8  VOUT_MODE (20h)
        1. Mode:
        2. Exponent
      9. 8.6.9  VIN_ON (35h)
        1. Exponent
        2. Mantissa
      10. 8.6.10 VIN_OFF (36h)
        1. Exponent
        2. Mantissa
      11. 8.6.11 IOUT_CAL_OFFSET (39h)
        1. Exponent
        2. Mantissa
      12. 8.6.12 IOUT_OC_FAULT_LIMIT (46h)
        1. Exponent
        2. Mantissa
      13. 8.6.13 IOUT_OC_FAULT_RESPONSE (47h)
        1. RS[2:0]
      14. 8.6.14 IOUT_OC_WARN_LIMIT (4Ah)
        1. Exponent
        2. Mantissa
      15. 8.6.15 OT_FAULT_LIMIT (4Fh)
        1. Exponent
        2. Mantissa
      16. 8.6.16 OT_WARN_LIMIT (51h)
        1. Exponent
        2. Mantissa
      17. 8.6.17 TON_RISE (61h)
        1. Exponent
        2. Mantissa
      18. 8.6.18 STATUS_BYTE (78h)
      19. 8.6.19 STATUS_WORD (79h)
      20. 8.6.20 STATUS_VOUT (7Ah)
      21. 8.6.21 STATUS_IOUT (7Bh)
      22. 8.6.22 STATUS_TEMPERATURE (7Dh)
      23. 8.6.23 STATUS_CML (7Eh)
      24. 8.6.24 STATUS_MFR_SPECIFIC (80h)
      25. 8.6.25 READ_VOUT (8Bh)
      26. 8.6.26 READ_IOUT (8Ch)
        1. Exponent
        2. Mantissa
      27. 8.6.27 READ_TEMPERATURE_2 (8Eh)
        1. Exponent
        2. Mantissa
      28. 8.6.28 PMBUS_REVISION (98h)
      29. 8.6.29 MFR_SPECIFIC_00 (D0h)
      30. 8.6.30 VREF_TRIM (MFR_SPECIFIC_04) (D4h)
      31. 8.6.31 STEP_VREF_MARGIN_HIGH (MFR_SPECIFIC_05) (D5h)
      32. 8.6.32 STEP_VREF_MARGIN_LOW (MFR_SPECIFIC_06) (D6h)
      33. 8.6.33 PCT_VOUT_FAULT_PG_LIMIT (MFR_SPECIFIC_07) (D7h)
      34. 8.6.34 SEQUENCE_TON_TOFF_DELAY (MFR_SPECIFIC_08) (D8h)
      35. 8.6.35 OPTIONS (MFR_SPECIFIC_21) (E5h)
      36. 8.6.36 MASK_SMBALERT (MFR_SPECIFIC_23) (E7h)
        1.  mOTFI
        2.  mPRTCL
        3.  mSMBTO
        4.  mIVC
        5.  mIVD
        6.  mPEC
        7.  mMEM
        8.  Auto_ARA
        9.  mOTF
        10. mOTW
        11. mOCF
        12. mOCW
        13. mOVF
        14. mUVF
        15. mPGOOD
        16. mVIN_UV
      37. 8.6.37 DEVICE_CODE (MFR_SPECIFIC_44) (FCh)
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Switching Frequency Selection
        2.  Inductor Selection
        3.  Output Capacitor Selection
          1. Response to a Load Transition
          2. Output Voltage Ripple
        4.  D-CAP Mode and D-CAP2 Mode Stability
        5.  Input Capacitor Selection
        6.  Bootstrap Capacitor and Resistor Selection
        7.  BP6, BP3 and BPEXT
        8.  R-C Snubber and VIN Pin High-Frequency Bypass
        9.  Temperature Sensor
        10. Key PMBus Parameter Selection
          1. Enable, UVLO and Sequencing
          2. Soft-Start Time
          3. Overcurrent Threshold and Response
          4. Power Good, Output Overvoltage and Undervoltage Protection
        11. Output Voltage Setting and Frequency Compensation Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Mounting and Thermal Profile Recommendation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. Texas Instruments Fusion Digital Power Designer
      2. 12.1.2 Device Nomenclature
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

Layout is a critical portion of good power supply design. The following layout recommendations will help guide you through a good layout of the TPS544B20 and TPS544C20 Devices. Figure 45 shows the recommended PCB layout configuration for additional reference.

  • As with any switching regulator, there are several signal paths that conduct fast switching voltages or currents. Minimize the loop area formed by these paths and their bypass connections.
  • Bypass the VIN pins to GND with a low-impedance path. Power-stage input bypass capacitors should be as close as physically possible to the VIN and GND pins. Additionally, a high-frequency bypass capacitor on the VIN pins can help to reduce switching spikes. See Figure 46 for placement recommendation.
  • The AGNDSNS pin must be kelvin connected to the AGND pin, with a low-noise, low-impedance path to ensure accurate current monitoring. This connection must be made on an internal or bottom layer. It should not segment the thermal tab copper area. This connection serves as the only connection between AGND and GND for this device.
  • Signal components should be terminated or bypassed to a separate analog ground (AGND) copper area, which is isolated from fast switching voltage and current paths. This copper area should not be connected to the thermal tab, or to an internal ground plane, and should be reserved for this regulator only.
  • Minimize the SW copper area for best noise performance. Route sensitive traces away from SW and BOOT, as these nets contain fast switching voltages, and lend easily to capacitive coupling.
  • Snubber component placement is critical to its effectiveness of ringing reduction. These components should be on the same layer as the devices, and be kept as close as possible to the SW and GND copper areas.
  • Keep signal components and regulator bypass capacitors local to the device, and place them as close as possible to the pins to which they are connected. These components include the feedback resistors, frequency compensation, the RRT resistor, ADDR0 and ADDR1 resistors, as well as bypass capacitors for BP3, BP6, VDD, and optionally BPEXT.
  • The VIN and VDD pins must be the same voltage for accurate short circuit protection, but high frequency switching noise on the VDD pin can degrade performance. VDD should be connected to VIN through a trace from the input copper area. To avoid high frequency noise on VDD, TI recommends keeping the VDD to VIN connection as short as possible to keep the parasitic inductance low. Optionally form a small low-pass R-C between VIN and VDD, with the VDD bypass capacitor (0.1 µF to 1.0 µF) and a 0-Ω to 2-Ω resistor between VIN and VDD. See Figure 45.
  • The VDD bypass capacitor can conduct high frequency switching currents. Thus in practice, TI recommends grounding the VDD bypass capacitor to GND or AGNDSNS rather than AGND. If AGNDSNS is used, to avoid injecting noise into the regulation path, it is important to route the ground return of the bypass capacitor to AGNDSNS through a dedicated trace to avoid sharing a path to AGND between the VDD capacitor and the FB to AGND (Rbias) resistor and COMP to AGND (Ccomp) capacitor.
  • The TPS544B20 and TPS544C20 devices have several pins which require good local bypassing. Place bypass capacitors as close as possible to the device pins, with a minimum return loop back to ground. Poor bypassing on VDD, BP3 and BP6 can degrade the performance of the regulator.
  • Route the VOUTS+ and VOUTS– lines from the output capacitor bank at the load back to the device pins as a tightly coupled differential pair. It is critical that these traces be kept away from switching or noisy areas which can add differential-mode noise.
  • Routing of the temperature sensor traces is critical to the noise performance of temperature monitoring. Keep these traces away from switching areas or high current paths on the layout. It is also recommended to use a small 1-nF capacitor from TSNS to AGND to improve the noise performance of temperature readings.

Layout Example

TPS544B20 TPS544C20 app_SLUS69B_layout2.gif Figure 45. PCB Layout Recommendation
TPS544B20 TPS544C20 app_SLUS69B_HF_bypass.gif Figure 46. High-Frequency Bypass Capacitor Placement

Mounting and Thermal Profile Recommendation

Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the reflow process can affect electrical performance. Figure 47 shows the recommended reflow oven thermal profile. Proper post-assembly cleaning is also critical to device performance. See SLUA271 for more information.

TPS544B20 TPS544C20 mech_thermal_profile.gif Figure 47. Recommended Reflow Oven Thermal Profile

Table 12. Recommended Thermal Profile Parameters

rRAMP(up) Average ramp-up rate, TS(max) to TP 3 °C/s
rRAMP(down) Average ramp-down rate, TP to TS(max) 6 °C/s
TS Pre-Heat temperature 150 200 °C
tS Pre-heat time, TS(min) to TS(max) 60 180 s
TL Liquidus temperature 217 °C
TP Peak temperature 260 °C
tL Time maintained above liquidus temperature, TL 60 150 s
tP Time maintained within 5 °C of peak temperature, TP 20 40 s
t25P Total time from 25 °C to peak temperature, TP 480 s