SLVSBI5A May   2013  – October 2014 TPS54531

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency PWM Control
      2. 8.3.2  Voltage Reference (Vref)
      3. 8.3.3  Bootstrap Voltage (BOOT)
      4. 8.3.4  Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
      5. 8.3.5  Programmable Slow Start Using SS Pin
      6. 8.3.6  Error Amplifier
      7. 8.3.7  Slope Compensation
      8. 8.3.8  Current-Mode Compensation Design
      9. 8.3.9  Overcurrent Protection and Frequency Shift
      10. 8.3.10 Overvoltage Transient Protection
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Eco-mode™
      2. 8.4.2 Operation With VIN < 3.5 V
      3. 8.4.3 Operation With EN Control
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency
        2. 9.2.2.2  Output Voltage Set Point
        3. 9.2.2.3  Undervoltage Lockout Set Point
        4. 9.2.2.4  Input Capacitors
        5. 9.2.2.5  Output Filter Components
          1. 9.2.2.5.1 Inductor Selection
          2. 9.2.2.5.2 Capacitor Selection
        6. 9.2.2.6  Compensation Components
        7. 9.2.2.7  Bootstrap Capacitor
        8. 9.2.2.8  Catch Diode
        9. 9.2.2.9  Slow-Start Capacitor
        10. 9.2.2.10 Output Voltage Limitations
        11. 9.2.2.11 Power Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Electromagnetic Interference (EMI) Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the source of the anode of the catch diode. Figure 25 shows a PCB layout example. The GND pin should be tied to the PCB ground plane at the pin of the device. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the exposed thermal pad should be soldered directly to the top-side ground area under the device. Use thermal vias to connect the top-side ground area to an internal or bottom-layer ground plane. The total copper area must provide adequate heat dissipation. Additional vias adjacent to the device can be used to improve heat transfer to the internal or bottom-layer ground plane . The additional external components can be placed approximately as shown. Obtaining acceptable performance with alternate layout schemes may be possible, however this layout has been shown to produce good results and is intended as a guideline.

11.2 Layout Example

layout_SLVSBI5.gifFigure 25. TPS54531DDA Board Layout

11.3 Electromagnetic Interference (EMI) Considerations

As EMI becomes a rising concern in more and more applications, the internal design of the TPS54531 device includes features to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used to lower the parasitics effects.

To achieve the best EMI performance, external component selection and board layout are equally important. Follow the steps listed in the Detailed Design Procedure section to prevent potential EMI issues.