10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast-changing currents or voltages that interact with stray inductance or parasitic capacitance to generate noise or degrade performance. To reduce parasitic effects, bypass the VIN pin to ground with a low-ESR ceramic bypass-capacitor with X5R or X7R dielectric. Minimize the loop area formed by the bypass-capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 73 for a PCB layout example. Tie the GND pin directly to the thermal pad under the IC.

Connect the thermal pad to internal PCB ground planes using multiple vias directly under the IC. Route the SW pin to the cathode of the catch diode and to the output inductor. Because the SW connection is the switching node, locate the catch diode and output inductor close to the SW pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, ensure the top-side ground area provides adequate heat dissipating area. The RT/CLK pin is sensitive to noise so locate and rout the RT resistor as close as possible to the IC with minimal lengths of trace, respectively. The additional external components are placed approximately as shown. Obtaining acceptable performance with alternate PCB layouts is possible, however this layout produces good results and TI intends it as a guideline.

10.2 Layout Example

Figure 73. PCB Layout Example

10.3 Estimated Circuit Area

Boxing in the components in the design of Figure 46 the estimated printed circuit board area is 1.025 in² (661 mm²). This area does not include test points or connectors.