SLVSCQ8A December   2015  – April 2016 TPS54A20

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Frequency Selection
      2. 7.3.2  External Clock Syncronization
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Soft Start
      5. 7.3.5  Startup into Pre-biased Outputs
      6. 7.3.6  Power Good (PGOOD)
      7. 7.3.7  Overcurrent Protection
      8. 7.3.8  Light Load Operation
      9. 7.3.9  Output Undervoltage/Overvoltage Protection
      10. 7.3.10 Input Undervoltage/Overvoltage Lockout
      11. 7.3.11 Enable and Adjusting Undervoltage Lockout
      12. 7.3.12 Series Capacitor Monitoring
        1. 7.3.12.1 Dropping Below 35% Threshold
        2. 7.3.12.2 Rising Above 65% Threshold
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Phase A Power Stage
      15. 7.3.15 Phase B Power Stage
      16. 7.3.16 Internal Gate Drive Regulator
      17. 7.3.17 Voltage Feed Forward
      18. 7.3.18 Internal Oscillator
      19. 7.3.19 Pulse Frequency Detector
      20. 7.3.20 On-Time Generator
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Two-Phase Series Capacitor Buck Converter Topology
      2. 8.1.2 Converter Switch Configurations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  On-Time
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor Selection
        6. 8.2.2.6  Input Capacitor Selection
        7. 8.2.2.7  Series Capacitor Selection
        8. 8.2.2.8  Soft-Start Time Selection
        9. 8.2.2.9  Bootstrap Capacitor Selection
        10. 8.2.2.10 Gate Drive Capacitor Selection
        11. 8.2.2.11 Under Voltage Lockout Set Point
        12. 8.2.2.12 Current Limit Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNJ|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input Voltage Power Conversion, VIN DC w.r.t. PGND, switching –0.3 15 V
DC w.r.t. PGND, non-switching –0.3 17
Bootstrap, V(BOOTA) DC with respect to PGND –0.3 22 V
DC with respect to SCAP 6 V
Bootstrap, V(BOOTB) DC with respect to PGND –0.3 14 V
DC with respect to SWB 6 V
Bias Supply, VG DC with respect to PGND –0.3 6 V
Series Capacitor Node Voltage, V(SCAP) DC with respect to PGND –0.3 16 V
Switch Node Voltage, V(SWA, SWB) DC with respect to PGND –1 9
Pulse < 10 ns –4 14
Feedback, V(FB) –0.3 3 V
Output Voltage Bias Supply, V(VGA) DC with respect to PGND –0.3 15 V
Voltage Enable Voltage, V(EN) –0.3 7 V
Soft Start/Freq. Select, V(SS/FSEl) –0.3 3
Power Good Voltage, V(PGOOD) –0.3 6
External Sync Clock Voltage, V(SYNC) –0.3 6
Current Limit/Mode Select, V(ILIM) –0.3 3
On Time Pin Voltage, V(TON) –0.3 3
Input Current Power Conversion, I(VIN) 6 A
Bias Supply, I(VG) 100 mA
Output Current Switch Node A, I(SWA) Current Limit A
Switch Node B, I(SWB) Current Limit A
Operating Junction Temperature, TJ –40 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input Voltage 8 14 V
VOUT Output Voltage 0.5 VIN/5 V
IOUT Output Current 0 10 A
TJ Junction Temperature -40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) RNJ UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 25(2) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 13.4 °C/W
RθJB Junction-to-board thermal resistance 4.9 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 4.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.0 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Tested on four layer evaluation board.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN VIN Operating 8 12 14 V
VIN Input UVLO Voltage VIN rising 7.4 7.65 7.95 V
VIN UVLO hysteresis 250 mV
VIN Input OVLO Voltage VIN rising 15.4 15.8 V
VIN falling 14.1 14.8 V
VIN OVLO hysteresis 600 mV
Shutdown EN < 0.4 V, VIN = 12 V, TA = 25°C 47 µA
IQ Operating into VIN FB = 0.53 V, VIN = 12 V, TA = 25°C 6 mA
ENABLE (EN PIN)
Enable threshold 1.17 1.23 1.27 V
Input current Enable threshold + 50 mV –4 µA
Enable threshold – 50 mV –1 µA
VOLTAGE REFERENCE
Voltage Reference TA = 25°C 0.5054 0.508 0.5106 V
–40°C < TJ < 125°C 0.5029 0.508 0.5131 V
FREQUENCY
fOSC Oscillator Frequency R(SS/FSEL) = Open, 71.5 kΩ,
or 48.7 kΩ		 3.6 4 4.4 MHz
R(SS/FSEL) = Short or 35.7 kΩ 6.3 7 7.7 MHz
R(SS/FSEL) = 21.5 kΩ, 15.4 kΩ,
or 8.66 kΩ		 9 10 11 MHz
SYNC
Minimum Input Clock Pulsewidth 20 ns
SYNC high threshold 2 V
SYNC low threshold 0.8 V
Frequency sync range ±10 % nominal
Last SYNC falling/rising edge to return to resistor timing mode if SYNC is not present 10 MHz: 400 ns
7 MHz: 571 ns
4 MHz : 1 µs		 4 Cycles
LOW-SIDE A MOSFET
On resistance VG = 5 V, Measured at pins 6.8 10.5 mΩ
LOW-SIDE B MOSFET
On resistance VG = 5 V, Measured at pins 9.3 14.8 mΩ
HIGH-SIDE MOSFETS
On resistance Vgs = 5 V, Measured at pins 27 50 mΩ
SW rise time 10% to 90% VIN = 12 V 2 ns
SW fall time 90% to 10% VIN = 12 V 2 ns
CURRENT LIMIT
Peak Switch LSA Current Limit ~15A Load Trip, R(ILIM) = Open 12.7 16.3 19.9 A
~11.25A Load Trip, R(ILIM) = 47 kΩ 9.9 12.7 15.5
Peak Switch LSB Current Limit ~15A Load Trip, R(ILIM) = Open 6.8 8.7 10.6 A
~11.25A Load Trip, R(ILIM) = 47 kΩ 5.3 6.8 8.3
Overcurrent protection scheme Hiccup
OCP cycle count to trip fault 3 Cycles
Fault hiccup wait time 10 MHz: 13.1 ms
7 MHz: 18.7 ms
4 MHz: 32.8 ms		 131,072 Cycles
INTERNAL REGULATOR (VG LDO)
Output Voltage 0 mA ≤ IVG ≤ 100 mA 4.4 4.8 5 V
Current Limit 100 140 mA
Nominal Operating Current Fosc = 10 MHz, ILOAD = 10A 60 mA
DYNAMIC REGULATOR (VGA LDO)
Output Voltage 15 V
VIN = 12 V 10.5 V
SERIES CAP MONITOR
Low Voltage Fault Trip 35 38 %VIN
Nominal Voltage 50
High Voltage Fault Trip 62 65
Capacitor Precharge Current 5.5 10 14.5 mA
POWER GOOD
VFB threshold VFB falling (Fault), UVP 90 %VREF
VFB rising (Good) 95
VFB rising (Fault), OVP 110
VFB falling (Good) 105
PGOOD sink current V(PGOOD) = 0.4 V 2.7 mA
PGOOD pin leakage current VFB = VREF, V(PGOOD)= 5 V 1 μA
Minimum VIN for valid PGOOD V(PGOOD) ≤ 0.5 V at 100 µA 1.2 2.75 V
THERMAL SHUTDOWN
Thermal shutdown set threshold 135 °C
Thermal shutdown hysteresis 20 °C
Thermal shutdown hiccup time 10 MHz: 13.1 ms
7 MHz: 18.7 ms
4 MHz: 32.8 ms		 131,072 Cycles

6.6 Timing Requirements

MIN NOM MAX UNIT
ENABLE (EN PIN)
Enable to Start Switching time 1 µF series cap, VIN = 12V 625 µs
SYNC
Lock in time 30 µs
HIGH-SIDE MOSFETS
SW minimum ON pulse width 14 ns
SW minimum OFF pulse width 10 ns
Non-Overlap Time between HS FET Off and LS FET On (deadtime) Fsw = 5 MHz, VIN = 12 V 3 ns
Non-Overlap Time between LS FET Off and HS FET On (deadtime) 3 ns

6.7 Typical Characteristics

VIN = 12 V, VOUT = 1.2 V, TA = 25 ºC, unless otherwise noted.
TPS54A20 D001_SLVSCQ8.gif
Figure 1. On Resistance vs Junction Temperature
TPS54A20 D003_SLVSCQ8.gif
Figure 3. On Resistance vs Junction Temperature
TPS54A20 D005_SLVSCQ8.gif
Figure 5. Oscillator Frequency vs Junction Temperature
TPS54A20 D007_SLVSCQ8.gif
Figure 7. Oscillator Frequency vs Junction Temperature
TPS54A20 D009_SLVSCQ8.gif
EN = Threshold + 50 mV
Figure 9. EN Pin Current vs Junction Temperature
TPS54A20 D011_SLVSCQ8.gif
Figure 11. EN Pin Threshold vs Junction Temperature
TPS54A20 D013_SLVSCQ8.gif
Figure 13. PGOOD and Under/Overvoltage Protection Threshold vs Junction Temperature
TPS54A20 D015_SLVSCQ8.gif
Figure 15. Phase B Low-Side MOSFET Current Limit vs Junction Temperature
TPS54A20 D100_SLVSCQ8.gif
Figure 17. Undervoltage Lockout Threshold vs Junction Temperature
TPS54A20 D022_SLVSCQ8.gif
fsw = 2 MHz per phase 3.2 x 2.5 x 1.2 mm inductors
Figure 19. Efficiency vs Output Current for Gate Drive Supply
TPS54A20 D023_SLVSCQ8.gif
fsw = 2 MHz per phase 3.2 x 2.5 x 1.2 mm inductors No air flow
Figure 21. Case Temperature Rise vs Output Current
TPS54A20 D025_SLVSCQ8.gif
Figure 23. Line Regulation
TPS54A20 D033_SLVSCQ8.gif
Figure 25. Min Input Voltage vs Output Voltage
TPS54A20 VinSweepVo3with1OhmLoad2Crop.png
1 Ω Load fsw = 2 MHz per phase
40 ms/div
Figure 27. Input UVLO and OVLO
TPS54A20 ENShutdownFCCMwPGOODw0p5ohmLoad.png
5 Ω Load fsw = 2 MHz per phase 40 µs/div
Figure 29. Shutdown Through EN
TPS54A20 VINStartup0AFCCMwPGOOD.png
Series capacitance = 1 µF fsw = 2 MHz per phase
2 ms/div
Figure 31. Startup Through VIN
TPS54A20 VINShutdownFCCMwILAw75ohmLoad.png
75 Ω Load 4 ms/div
Figure 33. Shutdown Through VIN
TPS54A20 ShortCircuitFCCM15A2.png
fsw = 2 MHz per phase 2 µs/div
Figure 35. Short Circuit Protection
TPS54A20 SteadyStateFCCM2MHz0A.png
fsw = 2 MHz per phase 0 A load 200 ns/div
Figure 37. Steady-State Waveforms
TPS54A20 ThermalShutdown.png
Figure 39. Thermal Shutdown
TPS54A20 10A2MHzExtVG.png
Room temperature 10 A load No air flow
fsw = 2 MHz per phase 3.2 x 2.5 x 1.2 mm inductors Four layer board
Figure 41. Thermal Image
TPS54A20 D002_SLVSCQ8.gif
Figure 2. On Resistance vs Junction Temperature
TPS54A20 D004_SLVSCQ8.gif
Figure 4. Voltage Reference vs Junction Temperature
TPS54A20 D006_SLVSCQ8.gif
Figure 6. Oscillator Frequency vs Junction Temperature
TPS54A20 D008_SLVSCQ8.gif
EN = 0 V
Figure 8. Shutdown Current vs Junction Temperature
TPS54A20 D010_SLVSCQ8.gif
EN = Threshold - 50 mV
Figure 10. EN Pin Current vs Junction Temperature
TPS54A20 D012_SLVSCQ8.gif
FB = 0.53 V (non-switching)
Figure 12. Non-Switching Operating Current vs Junction Temperature
TPS54A20 D014_SLVSCQ8.gif
Figure 14. Phase A Low-Side MOSFET Current Limit vs Junction Temperature
TPS54A20 D016_SLVSCQ8.gif
Figure 16. Internal Gate Drive Voltage (VG) vs Junction Temperature
TPS54A20 D018_SLVSCQ8.gif
Figure 18. Overvoltage Lockout Threshold vs Junction Temperature
TPS54A20 D034_SLVSCQ8.gif
fsw = 2 MHz per phase External VG+ 3.2 x 2.5 x 1.2 mm inductors
Figure 20. Efficiency vs Output Current for Output Voltage
TPS54A20 D024_SLVSCQ8.gif
Figure 22. Load Regulation
TPS54A20 D026_SLVSCQ8.gif
Figure 24. Max Output Voltage vs Input Voltage
TPS54A20 D027_SLVSCQ8.gif
i.
Figure 26. Frequency vs Output Current
TPS54A20 ENStartup0AFCCMwPGOOD.png
Series capacitance = 1 µF fsw = 2 MHz per phase
200 µs/div
Figure 28. Startup Through EN
TPS54A20 PrebiasENStartupFCCMw75ohmLoad.png
Series capacitance = 1 µF fsw = 2 MHz per phase
200 µs/div
Figure 30. Pre-biased Startup Through EN
TPS54A20 PrebiasVINStartupFCCMw0ALoad.png
0 A Load fsw = 2 MHz per phase 400 µs/div
Figure 32. Pre-biased Startup Through VIN
TPS54A20 VINShutdownFCCMwPGOODw0p5ohmLoad2.png
0.5 Ω Load 20 µs/div
Figure 34. Shutdown Through VIN
TPS54A20 ShortCircuitFCCM15Ahiccup.png
4 ms/div
Figure 36. Short Circuit Hiccup Restart
TPS54A20 SYNCaddRemove3p2MHz.png
3.2 MHz SYNC clock
Figure 38. External SYNC Add/Remove
TPS54A20 ThermalShutdownRecovery.png
Figure 40. Thermal Shutdown Recovery