SLIS132A October 2008 – March 2015 TPS55065-Q1
The TPS55065 is a buck/boost switched-mode regulator that operates in a power-supply concept to ensure a stable output voltage with input voltage excursions and specified load range.
The device provides an alarm indicator and reset output to interface with systems that require supervisory function.
The switching regulator offers a clock modulator and a current-mode slew-rate control for the internal switching transistor (Q1) to minimize EMI.
An internal low-rDS(on) switch has a current-limit feature to prevent inadvertent reset when turning on the 5-Vg output.
The external inductor for the switched-mode regulator is connected between terminals L1 and L2. This inductor is placed close to the terminals to minimize parasitic effects. For stability, use an inductor with 20 μH to 100 μH.
The input voltage of the device is connected to the Vdriver terminal. This input line requires a filter capacitor to minimize noise. TI recommends using a low-ESR aluminum or tantalum input capacitor. The relevant parameters for the input capacitor are the voltage rating and RMS current rating. The voltage rating should be approximately 1.5 times the maximum applied voltage for an aluminum capacitor and 2 times for a tantalum capacitor. In buck mode, the RMS current is , where D is the duty cycle and its maximum RMS current value is reached when D = 50% with IRMS = IOUT/2. In boost mode, the RMS current is 0.3 × ΔI, where ΔI is the peak-to-peak ripple current in the inductor. To achieve this, ESR ceramic capacitors are used in parallel with the aluminum or tantalum capacitors.
The Vlogic terminal is used to decouple the internal power-supply noise by use of a 470-nF capacitor. This terminal can also be used as an output supply for the logic-level inputs for this device (SCR0, SCR1, ENABLE, CLP, and 5Vg_ENABLE).
The AIN terminal is used to program the threshold voltage for monitoring and detecting undervoltage conditions on the input supply. A maximum of 40 V may be applied to this terminal and the voltage at this terminal may exceed the V(driver) input voltage without effecting the device operation. The resistor divider network is programmed to set the undervoltage detection threshold on this terminal (see the application schematic). The input has a typical hysteresis of 200 mV with a typical upper limit threshold of 2.5 V and a typical lower limit threshold of 2.3 V. When V(AIN) falls below 2.3 V, V(AOUT) is asserted low; when V(AIN) exceeds 2.5 V, V(AOUT) is in the high-impedance state.
The equations to set the upper and lower thresholds of V(AIN) are:
The AOUT terminal is an open-drain output that asserts low when the input voltage falls below the set threshold on the AIN input.
The REST terminal sets the desired delay time to assert the RESET terminal low after the 5-V supply has exceeded 4.65 V (typical). The delay can be programmed in the range of 2.2 ms to 150 ms using capacitors in the range of 2.2 nF to 150 nF. The delay time is calculated using Equation 2:
The RESET terminal is an open-drain output. The power-on reset output is asserted low until the output voltage exceeds the 4.65-V threshold and the reset delay timer has expired. Additionally, whenever the ENABLE terminal is low, RESET is immediately asserted low regardless of the output voltage.
The VOUT terminal is the output of the switched-mode regulated supply. This terminal requires a filter capacitor with low-ESR characteristics to minimize output ripple voltage. For stability, a capacitor with 22 μF to 470 μF should be used. The total capacitance at pin VOUT and pin 5Vg must be less than or equal to 470 μF.
The CLP terminal controls the low-power mode of the device. An external low digital signal switches the device to low-power mode or normal mode when the input is high.
The 5Vg terminal switches the 5-V regulated output. The output voltage of the regulator can be enabled or disabled using this low-rDS(on) internal switch. This switch has a current-limiting function to prevent generation of a reset signal at turnon caused by the capacitive load on the output or overload condition. When the switch is enabled, the regulated output may deviate and drop momentarily to a tolerance of 7% until the 5Vg capacitor is fully charged. This deviation depends on the characteristics of the capacitors on VOUT and 5Vg.
The 5Vg_ENABLE is a logic-level input for enabling the switch output on 5Vg.
For the functional terminal, see 5Vg_ENABLE results in Table 1:
|0||5Vg is off|
|Open (internal pulldown = 500 kΩ)||5Vg is off|
|1||5Vg is on|
The slew rate of the switching transistor Q1 is set using the SCR0 and SCR1 terminals.
Table 2 shows the values of the slew rate (SR):
See the converter efficiency plots in the Typical Characteristics section to determine power dissipation.
The Rmod terminal adjusts the clock modulator frequency. A resistor of Rmod = 12 kΩ generates a modulation frequency of 28 kHz. The modulator function may be disabled by connecting Rmod to GND and the device operates with the nominal frequency. The modulator function cannot be activated during IC operation, only at IC start-up.
The PGND terminal is the power ground for the device.
The ENABLE terminal allows the enabling and disabling of the switch mode regulator. A maximum of 40 V may be applied to this terminal to enable the device and increasing it above the V(driver) input voltage does not affect the device operation.
The functionality of the ENABLE terminal is described in Table 3:
|0||Vreg is off|
|1||Vreg is on|
An external bootstrap capacitor is required for driving the internal high-side MOSFET switch. A 4.7-nF ceramic capacitor is typically required.
To minimize EMI issues associated with the switched-mode regulator, the device offers an integrated clock modulator. The function of the clock modulator is to modulate the switching frequency and to distribute the energy over the wave band.
The average switching frequency is 440 kHz (typical) and varies between 330 kHz and 550 kHz at a rate set by the Rmod resistor. A typical value of 12 kΩ on the Rmod terminal relates to a 28-kHz modulation frequency. The clock modulator function can only be activated during IC start-up, not during IC operation.
The equation for the modulation frequency is as follows:
The operation mode switches automatically between buck and boost modes depending on the input voltage of V(driver) and output load conditions. During start up, when V(driver) is less than 5.8 V (typical), the device starts in boost mode and continues to run in boost mode until V(driver) exceeds 5.8 V; at which time, the device switches over to buck mode. In buck mode, the device continues to run in buck mode until it is required to switch back to boost to hold regulation. This crossover window to switch to boost mode is when V(driver) is between 5.8 V and 5 V and depends on the loading conditions. When Vdriver drops below 5.8 V but the device is holding regulation (~2%), the device remains in buck mode. However, when V(driver) is within the 5.8-V to 5-V window and VOUT drops to 4.9 V, the device crosses over to boost mode to hold regulation. In boost mode, the device remains in boost mode until V(driver) exceeds 5.8 V; at which time, the device enters the buck mode. When the device is operating in boost mode and V(driver) is in the crossover window of 5.8 V to 5 V, the output regulation may contain a higher than normal ripple and only maintain a 3% tolerance. This ripple and tolerance depends on the loading and improves with a higher loading condition. When the device is operated with low-power mode active (CLP = low) and high output currents (>50 mA), the buck/boost transitioning can cause a reset signal at the RESET pin.
In buck mode, the duty cycle of transistor Q1 sets the voltage VOUT. The duty cycle of transistor Q1 varies 10% to 99% depending on the input voltage, V(driver). If the peak inductor current (measured by Q1) exceeds 450 mA (typical), Q2 is turned on for this cycle (synchronized rectification). Otherwise, the current recirculates through Q2 as a free-wheeling diode. The detection for synchronous or asynchronous mode is done cycle-by-cycle.
To avoid a cross-conduction current between Q1 and Q2, an inherent delay is incorporated when switching Q1 off and Q2 on and vice versa.
In buck mode, transistor Q3 is not required and is switched off. Transistor Q4 is switched on to reduce power dissipation.
The switch timings for transistors Q3 and Q4 are not considered. In buck mode, the logical control of the transistors does not change.
In boost mode, the duty cycle of transistor Q3 controls the output voltage VOUT. The duty cycle is internally adjusted 5% to 85% depending on the internally sensed voltage of the output. Synchronized rectification occurs when V(driver) is below 5 V.
To avoid a discharging of the buffer capacitor, a simultaneous switching on of Q3 and Q4 is not allowed. An inherent delay is incorporated between Q3 switching off and Q4 switching on and vice versa.
In boost mode, transistor Q2 is not required and remains off. Transistor Q1 is switched on for the duration of the boost-mode operation (serves as a supply line).
The switch timings of transistors Q1 and Q2 are not considered. In boost mode, the logical control of the transistors does not change.
To ensure a stable 5-V output voltage with the output load in the specified range, the V(driver) supply must be greater than or equal to 5 V for greater than 1 ms (typical). After a period of 1 ms (typical), the logic may be supplied by the VOUT regulator and the V(driver) supply may be capable of operating down to 1.5 V.
The switched-mode regulator does not start at V(driver) less than 5 V.
To reduce quiescent current and to provide efficient operation, the regulator enters a pulsed mode.
The device enters this mode by a logic-level low on this terminal.
Automatic low-power mode is not available. The low-power-mode function is not available in boost mode. The device leaves low-power mode during boost mode regardless of the logic level on the CLP terminal.
To prevent thermal destruction, the device offers overtemperature protection to disable the IC. Also, short-circuit protection is included for added protection on VOUT and 5Vg.
A charge pump drives the internal FET, which switches the primary output voltage VOUT to the 5Vg pin. Protection is implemented to prevent the output voltage from dropping below its specified value while enabling the secondary output voltage. An explanation of the block diagram (see Figure 1) is given by the following example:
On power up, the device offers a soft-start feature which ramps the output of the regulator at a slew of 10 V/ms. When a reset occurs, the soft start is reenabled. Additionally, if the output capacitor is greater than 220 μF (typical), the slew rate decreases to a value set by the internal current limit. In boost mode, the soft-start feature is not active.