SLUSAH5D MARCH   2011  – February 2016 TPS56221

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Voltage Reference
      2. 7.3.2  Enable Functionality, Start-Up, Sequence, and Timing
        1. 7.3.2.1 COMP Pin Impedance Sensing
        2. 7.3.2.2 Overcurrent Protection (OCP) Setting
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Oscillator
      5. 7.3.5  Overcurrent Protection (OCP)
      6. 7.3.6  Switching Node (SW)
      7. 7.3.7  Input Undervoltage Lockout (UVLO)
      8. 7.3.8  Prebias Start-Up
      9. 7.3.9  Power Good
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency Selection
        2. 8.2.2.2  Inductor Selection
        3. 8.2.2.3  Output Capacitor Selection
        4. 8.2.2.4  Inductor Peak Current Rating
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Boot-Strap Capacitor (C14)
        7. 8.2.2.7  Boot-Strap Resistor (R2)
          1. 8.2.2.7.1 RC Snubber (R9 and C18)
        8. 8.2.2.8  VDD Bypass Capacitor (C11)
        9. 8.2.2.9  BP5 Bypass Capacitor (C12)
        10. 8.2.2.10 Soft-Start Capacitor (C13)
        11. 8.2.2.11 Current Limit (R1)
        12. 8.2.2.12 Feedback Divider (R4, R7)
        13. 8.2.2.13 Compensation (C15, C16, C17, R3, R6)
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQP|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TPS56221 is a 25-A high-performance synchronous buck converter with two integrated N-channel NexFET power MOSFETs. The device implements a voltage-mode control with voltage feed-forward compensation that responds instantly to input voltage change. Prebias capability eliminates concerns about damaging sensitive loads.

7.2 Functional Block Diagram

TPS56221 v11046_lusah5.gif

7.3 Feature Description

7.3.1 Voltage Reference

The 600-mV bandgap cell is internally connected to the noninverting input of the error amplifier. The reference voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final regulation voltage. The 1% tolerance on the reference voltage allows the user to design a very accurate power supply.

TPS56221 v11048_lusah5.gif Figure 19. Start-Up Sequence and Timing

7.3.2 Enable Functionality, Start-Up, Sequence, and Timing

After input power is applied, an internal 40-μA current source begins to charge the soft-start capacitor connected from EN/SS to GND. When the voltage across that capacitor increases to 0.7 V, it enables the internal BP regulator followed by a calibration. Total calibration time is approximately 1.9 ms. See Figure 19. During the calibration, the device performs the following two functions.

7.3.2.1 COMP Pin Impedance Sensing

The device samples the impedance at the COMP pin and determines the appropriate operating switching frequency. If there is no resistor connected from the COMP pin to GND, the switching frequency is set to the default value of 500 kHz. If a resistor of 40.2 kΩ ± 10% is connected from the COMP pin to GND, the switching frequency is set to 300 kHz. Alternatively, if a resistor of 13.3 kΩ ± 10% is connected from the COMP pin to GND, the switching frequency is set to 1 MHz.

After a 1.1-ms time period, the COMP pin is then brought low for 0.8 ms. This ensures that the feedback loop is preconditioned at start-up and no sudden output rise occurs at the output of the converter when it is allowed to start switching.

7.3.2.2 Overcurrent Protection (OCP) Setting

The device sources 10 μA (typical) to the resistor connected from the ILIM pin to GND. The voltage developed across that resistor multiplied by a factor of 2 is then sampled and latched off internally as the OCP trip level for the low-side FET until one cycles the input or toggles the EN/SS.

The voltage at EN/SS is internally clamped to 1.3 V before and/or during calibration to minimize the discharging time once calibration is complete. The discharging current is from an internal current source of 140 μA and it pulls the voltage down to 0.4 V. It then initiates the soft-start by charging up the capacitor using an internal current source of 10 μA. The resulting voltage ramp on this pin is used as a second noninverting input to the error amplifier after an 800 mV (typical) downward level-shift; therefore, the actual soft-start does not take place until the voltage at this pin reaches 800 mV.

If the EN/SS pin is left floating, the controller starts automatically. EN/SS must be pulled down to less than 270 mV to ensure that the chip is in shutdown mode.

7.3.3 Soft-Start Time

The soft-start time of the TPS56221 is user programmable by selecting a single capacitor. The EN/SS pin sources 10 μA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the 10 μA to charge the capacitor through a 600 mV range. There is some initial lag due to calibration and an offset (800 mV) from the actual EN/SS pin voltage to the voltage applied to the error amplifier.

The soft-start is accomplished in a closed-loop, meaning that the error amplifier controls the output voltage at all times during the soft-start period and the feedback loop is never open as occurs in duty cycle limit soft-start schemes. The error amplifier has two noninverting inputs, one connected to the 600-mV reference voltage, and the other connected to the offset EN/SS pin voltage. The lower of these two voltages is what the error amplifier controls the FB pin to. As the voltage on the EN/SS pin ramps up past approximately 1.4 V (800 mV offset voltage plus the 600 mV reference voltage), the 600-mV reference voltage becomes the dominant input and the converter has reached its final regulation voltage.

The capacitance required for a given soft-start ramp time for the output voltage is calculated in Equation 1.

Equation 1. TPS56221 q_css_lusah5.gif

where

  • CSS is the required capacitance on the EN/SS pin (nF)
  • ISS is the soft-start source current (10 μA)
  • VFB is the feedback reference voltage (0.6 V)
  • tSS is the desired soft-start ramp time (ms)

7.3.4 Oscillator

The oscillator frequency is internally fixed at 500 kHz if there is no resistor connected from COMP pin to GND. Optionally, a 40.2-kΩ resistor from the COMP pin to GND sets the frequency to 300 kHz. Alternatively, a 13.3-kΩ resistor from COMP pin GND sets the frequency to 1 MHz.

7.3.5 Overcurrent Protection (OCP)

Programmable OCP level at ILIM is from 6 mV to 50 mV. With a scale factor of 2, the actual OC trip point across the low-side FET is in the range of 12 mV to 100 mV.

If the voltage drop across ROCSET reaches 300 mV during calibration (No ROCSET resistor included), it disables OC protection. Once disabled, there is no low-side or high-side current sensing.

OCP level for the high-side FET is fixed at 54 A (typical). The high-side OCP provides pulse-by-pulse current limiting.

OCP sensing for the low-side FET is a true inductor valley current detection, using sample and hold. Equation 2 can be used to calculate ROCSET:

Equation 2. TPS56221 q_rocset_lusah5.gif

where

  • IP-P is the peak-to-peak inductor current (A)
  • IOUT(max) is the trip point for OCP (A)
  • ROCSET is the resistor used for setting the OCP level (Ω)

An overcurrent (OC) condition is detected by sensing voltage drop across the low-side FET and across the high-side FET. If the voltage drop across either FET exceeds OC threshold, a count increments one count. If no OC condition is detected on either FET, the fault counter decrements by one counter. If three OC pulses are summed, a fault condition is declared which cycles the soft-start function in a hiccup mode. Hiccup mode is defined as four dummy soft-start time-outs followed by a real one if overcurrent condition is encountered during normal operation; or five dummy soft-start time-outs followed by a real one if overcurrent condition occurs from the beginning during start. This cycle continues indefinitely until the fault condition is removed.

7.3.6 Switching Node (SW)

The SW pin connects to the switching node of the power conversion stage. It acts as the return path for the high-side gate driver. When configured as a synchronous buck stage, the voltage swing on SW normally traverses from below ground to well above the input voltage. Parasitic inductance in the high-side FET and the output capacitance (COSS) of both power FETs form a resonant circuit that can produce high frequency ( > 100 MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the pin.

In many cases, a series resistor and capacitor snubber network connected from the switching node to PGND can be helpful in damping the ringing and decreasing the peak amplitude. Provide provisions for snubber network components in the layout of the printed circuit board. If testing reveals that the ringing amplitude at the SW pin exceeds the limit, then include snubber components.

Placing a BOOT resistor with a value from 5 Ω to 10 Ω in series with the BOOT capacitor slows down the turnon of the high-side FET and can help to reduce the peak ringing at the switching node.

7.3.7 Input Undervoltage Lockout (UVLO)

The TPS56221 has fixed input UVLO. In order for the device to turn on, the following conditions must be met:

  • The EN/SS pin voltage must be greater than VIH
  • The input voltage must exceed UVLO on voltage VUVLO

The UVLO has a minimum of 500 mV hysteresis built-in.

7.3.8 Prebias Start-Up

The TPS56221 contains a unique circuit to prevent current from being pulled from the output during start-up in the condition the output is prebiased. There are no PWM pulses until the internal soft-start voltage rises above the error amplifier input (FB pin), if the output is prebiased. Once the soft-start voltage exceeds the error amplifier input, the controller slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow on time. It then increments the on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1–D), where D is the duty cycle of the converter.

This approach prevents the sinking of current from a prebiased output, and ensures the output voltage start-up and ramp to regulation is smooth and controlled.

7.3.9 Power Good

The TPS56221 provides an indication that output is good for the converter. This is an open-drain signal and pulls low when any condition exists that would indicate that the output of the supply might be out of regulation. These conditions include:

  • VFB is more than ±12.5% from nominal
  • soft-start function is active
  • a short-circuit condition has been detected

NOTE

When there is no power to the device, PGOOD cannot pull close to GND if an auxiliary supply is used for the power good indication. In this case, a built-in resistor connected from drain to gate on the PGOOD pulldown device makes the PGOOD pin look approximately like a diode to GND.

7.3.10 Thermal Shutdown

If the junction temperature of the device reaches the thermal shutdown limit of 145°C, both high-side FET and low-side FET are kept off. When the junction cools to the required level (125°C typical), the PWM initiates soft start as during a normal power-up cycle.

7.4 Device Functional Modes

The TPS56221 devices operate in continuous conduction mode (CCM) at a fixed frequency, regardless of the output current. For the first 128 switching cycles, the low-side MOSFET on-time is slowly increased to prevent excessive current sinking in the event the device is started with a prebiased output. Following the first 128 switching cycles, the low-side MOSFET and the high-side MOSFET on-times are fully complementary.