SLUSES9 July   2022 TPS563300

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Peak Current Mode
      2. 7.3.2  Pulse Frequency Modulation
      3. 7.3.3  Voltage Reference
      4. 7.3.4  Output Voltage Setting
      5. 7.3.5  Enable and Adjusting Undervoltage Lockout
      6. 7.3.6  Minimum On Time, Minimum Off Time, and Frequency Foldback
      7. 7.3.7  Frequency Spread Spectrum
      8. 7.3.8  Overvoltage Protection
      9. 7.3.9  Overcurrent and Undervoltage Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes Overview
      2. 7.4.2 Heavy Load Operation
      3. 7.4.3 Light-Load Operation
      4. 7.4.4 Dropout Operation
      5. 7.4.5 Minimum On-Time Operation
      6. 7.4.6 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Resistors Selection
        3. 8.2.2.3 Bootstrap Capacitor Selection
        4. 8.2.2.4 Undervoltage Lockout Set Point
        5. 8.2.2.5 Output Inductor Selection
        6. 8.2.2.6 Output Capacitor Selection
        7. 8.2.2.7 Input Capacitor Selection
        8. 8.2.2.8 Feedforward Capacitor CFF Selection
        9. 8.2.2.9 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 8-Pin SOT583DRL Package(Top View)
Table 5-1 Pin Functions
Pin Type(1) Description
Name NO.
NC 1 A Reserved pin. The user must leave this pin floating.
EN 2 A Enable input to converter. Driving EN high or leaving this pin floating enables the converter. An external resistor divider can be used to implement an adjustable VIN UVLO function.
VIN 3 P Supply input pin to the internal LDO and high-side FET. Input bypass capacitors must be directly connected to this pin and GND.
GND 4 G Ground pin. Connected to the source of the low-side FET as well as the ground pin for the controller circuit. Connect to system ground and the ground side of CIN and COUT. The path to CIN must be as short as possible.
SW 5 P Switching output of the convertor. Internally connected to the source of the high-side FET and drain of the low-side FET. Connect to the power inductor.
BST 6 P Bootstrap capacitor connection for the high-side FET driver. Connect a high-quality, 100-nF ceramic capacitor from this pin to the SW pin.
NC 7 A Reserved pin. The user must leave this pin floating.
FB 8 A Output feedback input. Connect FB to the tap of an external resistor divider from the output to GND to set the output voltage.
(1) A = Analog, P = Power, G = Ground