SLVSDU5A April   2018  – November 2019 TPS57112C-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency vs Output Current
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics Curves
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope Compensation and Output Current
      3. 7.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
        1. 7.3.3.1 Error Amplifier
      4. 7.3.4 Voltage Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adjusting the Output Voltage
      2. 7.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 7.4.3  Slow-Start or Tracking Pin
      4. 7.4.4  Sequencing
      5. 7.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 7.4.6  Overcurrent Protection
      7. 7.4.7  Frequency Shift
      8. 7.4.8  Reverse Overcurrent Protection
      9. 7.4.9  Synchronize Using the RT/CLK Pin
      10. 7.4.10 Power Good (PWRGD Pin)
      11. 7.4.11 Overvoltage Transient Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Small-Signal Model for Loop Response
      14. 7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
      15. 7.4.15 Small-Signal Model for Frequency Compensation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Switching Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Slow-Start Capacitor
        6. 8.2.2.6 Bootstrap Capacitor Selection
        7. 8.2.2.7 Output Voltage and Feedback Resistor Selection
        8. 8.2.2.8 Compensation
        9. 8.2.2.9 Power-Dissipation Estimate
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application Curves

TPS57112C-Q1 eff_cur_SLVSAL8.gif
Figure 35. Efficiency versus Load Current
TPS57112C-Q1 eff2_LVSAL8.gif
V(VIN) = 3.3 V f(SW) = 1 MHz TA = 25ºC
Figure 37. Efficiency versus Load Current
1 MHz, 3.3 VIN, TA = 25°C
TPS57112C-Q1 eff2_cur_SLVSAL8.gif
Figure 36. Efficiency versus Load Current
TPS57112C-Q1 eff1_SLVSAL8.gif
V(VIN) = 5 V f(SW) = 1 MHz TA = 25ºC
Figure 38. Efficiency versus Load Current
1 MHz, 5 VIN, TA = 25°C
TPS57112C-Q1 pwr_up_SLVSAH5.gifFigure 39. Power-Up VO, V(VIN)
TPS57112C-Q1 transient_ds_SLVSAH5.gifFigure 41. Transient Response, 1.5-A Step
TPS57112C-Q1 Start_en_ds_SLVSAH5.gifFigure 43. Power-Up VO, EN
TPS57112C-Q1 Vin_rip_lvsal8.gifFigure 45. Input Ripple, 2 A
TPS57112C-Q1 reg_cur_SLVSAL8.gif
Figure 47. Load Regulation versus Load Current
TPS57112C-Q1 pwr_dwn_SLVSAH5.gifFigure 40. Power-Down VO, V(VIN)
TPS57112C-Q1 ST_VIN_ds_SLVSAH5.gifFigure 42. Power-Up VO, V(VIN)
TPS57112C-Q1 Vout_rip_ds_SLVSAH5.gifFigure 44. Output Ripple, 2 A
TPS57112C-Q1 loop_resp_SLVSAH5.gif
Figure 46. Closed-Loop Response, V(VIN) (5 V), 2 A
TPS57112C-Q1 reg_vi_slvsah5c.gif
IO = 2 A
Figure 48. Regulation versus Input Voltage