SLVSCG0 July   2014 TPS57114-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Description (continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Fixed-Frequency Pwm Control
      2. 9.3.2  Slope Compensation and Output Current
      3. 9.3.3  Bootstrap Voltage (Boot) and Low-Dropout Operation
      4. 9.3.4  Error Amplifier
      5. 9.3.5  Voltage Reference
      6. 9.3.6  Adjusting the Output Voltage
      7. 9.3.7  Enable Functionality and Adjusting UVLO
      8. 9.3.8  Slow-Start or Tracking Pin
      9. 9.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      10. 9.3.10 Overcurrent Protection
      11. 9.3.11 Frequency Shift
      12. 9.3.12 Reverse Overcurrent Protection
      13. 9.3.13 Synchronize Using the RT/CLK Pin
      14. 9.3.14 Power Good (PWRGD Pin)
      15. 9.3.15 Overvoltage Transient Protection (OVTP)
      16. 9.3.16 Thermal Shutdown
      17. 9.3.17 Small-Signal Model for Loop Response
      18. 9.3.18 Simple Small-Signal Model for Peak-Current Mode Control
      19. 9.3.19 Small-Signal Model for Frequency Compensation
    4. 9.4 Device Functional Modes
      1. 9.4.1 RT (Resistor Timing) Mode
      2. 9.4.2 CLK (External Clock) Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Sequencing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting the Switching Frequency
        2. 10.2.2.2 Output Inductor Selection
        3. 10.2.2.3 Output Capacitor
        4. 10.2.2.4 Input Capacitor
        5. 10.2.2.5 Slow-Start Capacitor
        6. 10.2.2.6 Bootstrap Capacitor Selection
        7. 10.2.2.7 Output-Voltage and Feedback-Resistor Selection
        8. 10.2.2.8 Compensation
        9. 10.2.2.9 Power-Dissipation Estimate
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Description (continued)

Frequency foldback and thermal shutdown protect the device during an overcurrent condition.

The SwitcherPro™ software tool, available at www.ti.com/switcherpro, supports the TPS57114-EP.

For more SWIFT™ documentation, see the TI website at www.ti.com/swift.

TPS57114-EP is a current mode controller used to support various topologies such as buck converter configuration.

Current mode control is a two-loop system. The switching power supply inductor is hidden within the inner current control loop. This simplifies the design of the outer voltage control loop and improves power supply performance in many ways, including better dynamics. The objective of this inner loop is to control the state-space averaged inductor current, but in practice, the instantaneous peak inductor current is the basis for control (switch current—equal to inductor current during the on time—is often sensed). If the inductor ripple current is small, peak inductor current control is nearly equivalent to average inductor current control.

The peak method of inductor current control functions by comparing the upslope of inductor current (or switch current) to a current program level set by the outer loop. The comparator turns the power switch off when the instantaneous current reaches the desired level. The current ramp is usually quite small compared to the programming level, especially when VIN is low. As a result, this method is extremely susceptible to noise. A noise spike is generated each time the switch turns on. A fraction of a volt coupled into the control circuit can cause it to turn off immediately, resulting in a subharmonic operating mode with much greater ripple. Circuit layout and bypassing are critically important to successful operation.

The peak current mode control method is inherently unstable at duty ratios exceeding 0.5, resulting in subharmonic oscillation. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. Slope compensation must be added to the sensed current waveform or subtracted from the control voltage to ensure stability above a 50% duty cycle. A compensating ramp (with slope equal to the inductor current downslope) is usually applied to the comparator input to eliminate this instability. Current limit control design has numerous advantages:

  • Current mode control provided peak switch current limiting – pulse-by-pulse current limit.
  • The control loop is simplified as one pole because the output inductor is pushed to higher frequency, thus a two-pole system turns into two real poles. Thus, the system reduces to a first-order system and simplifies the control.
  • Multiple converters can be paralleled and allow equal current sharing amount the various converters.
  • Inherently provides for input voltage feed-forward because any perturbation in the input voltage is reflected in the switch or inductor current. Because switch or inductor current is a direct-control input, this perturbation is rapidly corrected.
  • The error amplifier output (outer control loop) defines the level at which the primary current (inner loop) regulates the pulse duration and output voltage.