SNVSA40A October   2014  – March 2016 TPS61169

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Soft Start-Up
      2. 8.3.2 Open LED Protection
      3. 8.3.3 Shutdown
      4. 8.3.4 Current Program
      5. 8.3.5 LED Brightness Dimming
      6. 8.3.6 Undervoltage Lockout
      7. 8.3.7 Thermal Foldback and Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With CTRL
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Schottky Diode Selection
        3. 9.2.2.3 Output Capacitor Selection
        4. 9.2.2.4 LED Current Set Resistor
        5. 9.2.2.5 Thermal Considerations
    3. 9.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage(2) VIN, CTRL, PWM, FB –0.3 7 V
SW –0.3 40
PD Continuous power dissipation See Thermal Information Table
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VIN Input voltage 2.7 5.5 V
VOUT Output voltage VIN 38 V
L Inductor 4.7 10 µH
CI Input capacitor 1 µF
CO Output capacitor 1 10 µF
FPWM PWM dimming signal frequency 5 100 kHz
DPWM PWM dimming signal duty cycle 1% 100%
TJ Operating junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS61169 UNIT
DCK (SC70)
5 PINS
RθJA Junction-to-ambient thermal resistance(2) 263.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(3) 76.1 °C/W
RθJB Junction-to-board thermal resistance(4) 51.4 °C/W
ψJT Junction-to-top characterization parameter(5) 1.1 °C/W
ψJB Junction-to-board characterization parameter(6) 50.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).

7.5 Electrical Characteristics

Over operating free-air temperature range, VIN = 3.6 V, CTRL = VIN (unless otherwise specified).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input voltage range 2.7 5.5 V
VVIN_UVLO Undervoltage lockout threshold VIN falling
VIN rising 		2 2.3
2.6 		V
VVIN_HYS VIN UVLO hysteresis 200 mV
IQ_VIN Operating quiescent current into VIN Device enable, switching 1.2 MHz and no load,
0.3 0.45 mA
ISD Shutdown current CTRL = GND 1 2 µA
CONTROL LOGIC AND TIMING
VH CTRL Logic high voltage 1.2 V
VL CTRL Logic Low voltage 0.4 V
RPD CTRL pin internal pull-down resistor 300 KΩ
tSD CTRL logic low time to shutdown CTRL high to low 2.5 ms
VOLTAGE AND CURRENT REGULATION
VREF Voltage feedback regulation voltage Duty = 100%, TA ≥ 25°C 188 204 220 mV
IFB FB pin bias current VFB = 204 mV 2.5 µA
tREF VREF filter time constant 1 ms
POWER SWITCH
RDS(ON) N-channel MOSFET on-resistance 0.35 0.7 Ω
ILN_NFET N-channel leakage current VSW = 35 V 1 µA
SWITCHING FREQUENCY
ƒSW Switching frequency VIN = 3 V 0.75 1.2 1.5 MHz
PROTECTION AND SOFT START
ILIM Switching MOSFET current limit D = DMAX , TA ≤ 85°C 1.2 1.8 2.4 A
ILIM_Start Switching MOSFET start-up current limit TA ≤ 85°C 0.72 A
tHalf_LIM Time step for half current limit 6.5 ms
VOVP_SW Output voltage overvoltage threshold 36 37.5 39 V
THERMAL SHUTDOWN
Tshutdown Thermal shutdown threshold 160 °C
Thys Thermal shutdown hysteresis 15 °C

7.6 Typical Characteristics

At TA = 25°C, unless otherwise noted.
TPS61169 D001_SNVSA40.gif
Figure 1. FB Voltage vs Dimming Duty Cycle
TPS61169 D002_SNVSA40.gif
Figure 2. Current Limit vs Temperature