SLVSAN6B February   2011  – September 2016 TPS61181A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Supply Voltage
      2. 8.3.2 Boost Regulator
      3. 8.3.3 Enable and Start-Up
      4. 8.3.4 Overcurrent, Overvoltage, and Short-Circuit Protection
      5. 8.3.5 IFB Pin Unused
    4. 8.4 Device Functional Modes
      1. 8.4.1 Current Program and PWM Dimming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Audible Noise Reduction
        4. 9.2.2.4 Isolation MOSFET Selection
      3. 9.2.3 Application Curves
    3. 9.3 Additional Application Circuits
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device And Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RTE Package
16-Pin WQFN
Top View
TPS61181A po_lvsan6.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 PGND I Power ground of the device. Internally, it connects to the source of the PWM switch.
2 SW I This pin connects to the drain of the internal PWM switch, external Schottky diode and inductor.
3 VBAT I This pin is connected to the battery supply. It provides the pullup voltage for the Fault pin and battery voltage signal. This is also the input to the internal LDO.
4 VO O This pin monitors the output of the boost regulator. Connect this pin to the anode of the WLED strings.
5 ISET I The resistor on this pin programs the WLED output current.
6 Cin I Supply voltage of the device. It is the output of the internal LDO. Connect 0.1-μF bypass capacitor to this pin.
7, 8, 9
12, 13, 14		 IFB1-IFB3
IFB4-IFB6		 I Current sink regulation inputs. They are connected to the cathode of WLEDs. The PWM loop regulates the lowest VIFB to 400  mV. Each channel is limited to 30-mA current.
10 GND I Signal ground of the device.
11 DCTRL I Dimming control logic input. The dimming frequency range is 100 Hz to 1 kHz.
15 EN I The enable pin to the device. A logic high signal turns on the internal LDO and enables the device. Therefore, do not connect the EN pin to the Cin pin.
16 Fault I Gate driver output for an external PFET used for fault protection. It can also be used as signal output for system fault report.