SLVSHH0 June   2026 TPS61290

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting
      2. 7.3.2 Switching Frequency and Spread Spectrum Function
    4. 7.4 Device Functional Modes
      1. 7.4.1  Enable and Start-Up
      2. 7.4.2  Operation Mode Setting
      3. 7.4.3  Bypass Mode
      4. 7.4.4  Boost Control Operation
      5. 7.4.5  Auto PFM Mode
      6. 7.4.6  Forced PWM Mode
      7. 7.4.7  Output Discharge
      8. 7.4.8  Undervoltage Lockout
      9. 7.4.9  Current Limit Operation
      10. 7.4.10 Output Short-to-Ground Protection
      11. 7.4.11 Thermal Shutdown
      12. 7.4.12 Power-Good Indication Status
    5. 7.5 Programming
      1. 7.5.1 Data Validity
      2. 7.5.2 START and STOP Conditions
      3. 7.5.3 Byte Format
      4. 7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 7.5.5 Target Address and Data Direction Bit
      6. 7.5.6 Single Read and Write
      7. 7.5.7 Multi-Read and Multi-Write
  9. 8 Register Maps
    1. 8.1 DeviceID Register
    2. 8.2 CONFIG Register
    3. 8.3 VOUTFLOORSET Register
    4. 8.4 ILIMBSTSET Register
    5. 8.5 VOUTROOFSET Register
    6. 8.6 STATUS Register
    7. 8.7 ILIMPTSET Register
    8. 8.8 BSTLOOP Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TPS61290x With 2.5V – 4.35V VIN, 3.4V VOUT, 6A Output Current
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Inductor Selection
          2. 9.2.1.2.2 Output Capacitor
          3. 9.2.1.2.3 Input Capacitor
          4. 9.2.1.2.4 Checking Loop Stability
        3. 9.2.1.3 Application Curves
      2. 9.2.2 TPS61290x With 2.5V – 4.85V VIN, 5.0V VOUT, 4A Output Current
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Information
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     81

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBG|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte is successfully received and another byte can be sent. All clock pulses, including the acknowledge ninth clock pulse, are generated by the controller.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line to low level and the SDA line remains stable low level during the high level period of this clock pulse.

The Not Acknowledge signal is when SDA remains high level during the ninth clock pulse. The controller can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.