SLVSET0D May   2020  – October 2021 TPS61378-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VCC Power Supply
      2. 8.3.2  Input Undervoltage Lockout (UVLO)
      3. 8.3.3  Enable and Soft Start
      4. 8.3.4  Shut Down
      5. 8.3.5  Switching Frequency Setting
      6. 8.3.6  Spread Spectrum Frequency Modulation
      7. 8.3.7  Adjustable Peak Current Limit
      8. 8.3.8  Bootstrap
      9. 8.3.9  Load Disconnect
      10. 8.3.10 MODE/SYNC Configuration
      11. 8.3.11 Overvoltage Protection (OVP)
      12. 8.3.12 Output Short Protection/Hiccup
      13. 8.3.13 Power-Good Indicator
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced PWM Mode
      2. 8.4.2 Auto PFM Mode
      3. 8.4.3 External Clock Synchronization
      4. 8.4.4 Down Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 Setting the Switching Frequency
        3. 9.2.2.3 Setting the Current Limit
        4. 9.2.2.4 Selecting the Inductor
        5. 9.2.2.5 Selecting the Output Capacitors
        6. 9.2.2.6 Selecting the Input Capacitors
        7. 9.2.2.7 Loop Stability and Compensation
          1. 9.2.2.7.1 Small Signal Model
          2. 9.2.2.7.2 Loop Compensation Design Steps
          3. 9.2.2.7.3 Selecting the Bootstrap Capacitor
          4. 9.2.2.7.4 VCC Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Thermal Information

THERMAL METRIC(1) TPS61378-Q1 UNIT
RTE
16 PINS
RθJA Junction-to-ambient thermal resistance 46.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 43.5 °C/W
RθJB Junction-to-board thermal resistance 18.5 °C/W
ψJT Junction-to-top characterization parameter 1.1 °C/W
ψJB Junction-to-board characterization parameter 18.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.