SUPPLY CURRENT |
VI |
Input voltage |
|
2.7 |
|
10 |
V |
I(Q) |
Operating quiescent current |
IO = 0 mA, SYNC = GND, VI = 7.2 V |
|
12 |
20 |
µA |
I(SD) |
Shutdown current |
EN = GND |
|
1.5 |
5 |
µA |
EN = GND, TA = 25°C |
|
1.5 |
3 |
IQ(LBI) |
Quiescent current with enhanced LBI comparator version. |
EN = VI, LBI = GND, TPS62051 only |
|
5 |
|
µA |
ENABLE |
VIH |
EN high level input voltage |
|
1.3 |
|
|
V |
VIL |
EN low level input voltage |
|
|
|
0.3 |
V |
|
EN trip point hysteresis |
|
|
100 |
|
mV |
Ilkg |
EN input leakage current |
EN = GND or VIN, VI = 7.2 V |
|
0.01 |
0.2 |
µA |
I(EN) |
EN input current |
0.6 V ≤ V(EN) ≤ 4 V |
|
2 |
|
µA |
V(UVLO) |
Undervoltage lockout threshold |
|
|
1.6 |
|
V |
POWER SWITCH |
RDS(ON) |
P-channel MOSFET ON-resistance |
VI ≥ 5.4 V; IO = 300 mA |
|
400 |
650 |
mΩ |
VI = 2.7 V; IO = 300 mA |
|
600 |
850 |
|
P-channel MOSFET leakage current |
VDS = 10 V |
|
|
1 |
µA |
|
P-channel MOSFET current limit |
VI = 7.2V, VO = 3.3 V |
1000 |
1200 |
1400 |
mA |
RDS(ON) |
N-channel MOSFET ON-resistance |
VI ≥ 5.4 V; IO = 300 mA |
|
300 |
450 |
mΩ |
VI = 2.7 V; IO = 300 mA |
|
450 |
550 |
|
N-channel MOSFET leakage current |
VDS = 6 V |
|
|
1 |
µA |
POWER GOOD OUTPUT, LBI, LBO |
V(PG) |
Power good trip voltage |
|
Vml –2% |
V |
|
Power good delay time |
VO ramping positive |
|
50 |
|
µs |
VO ramping negative |
|
200 |
|
VOL |
PG, LBO output low voltage |
V(FB) = 0.8 × VO nominal, I(sink) = 1 mA |
|
|
0.3 |
V |
|
PG, LBO output leakage current |
V(FB) = VO nominal, V(LBI) = VI |
|
0.01 |
0.25 |
µA |
|
Minimum supply voltage for valid power good, LBO signal |
|
|
2.3 |
|
V |
V(LBI) |
Low-battery input trip voltage |
Input voltage falling |
|
1.21 |
|
V |
|
Low-battery input trip point accuracy |
|
|
|
1.5% |
|
V(LBI,HYS) |
Low-battery input hysteresis |
|
|
15 |
|
mV |
Ilkg(LBI) |
LBI leakage current |
|
|
0.01 |
0.1 |
µA |
OSCILLATOR |
fS |
Oscillator frequency |
|
600 |
850 |
1000 |
kHz |
f(SYNC) |
Synchronization range |
|
600 |
|
1200 |
kHz |
VIH |
SYNC high-level input voltage |
|
1.5 |
|
|
V |
VIL |
SYNC low-level input voltage |
|
|
|
0.3 |
V |
Ilkg |
SYNC input leakage current |
SYNC = GND or VIN |
|
0.01 |
0.1 |
µA |
|
SYNC trip point hysteresis |
|
|
100 |
|
mV |
|
Duty cycle of external clock signal |
|
20% |
|
90% |
|
OUTPUT |
VO |
Adjustable output voltage |
TPS62050, TPS62051 |
|
0.7 |
|
6 |
V |
V(FB) |
Feedback voltage |
TPS62050, TPS62051 |
|
|
0.5 |
|
V |
|
FB leakage current |
TPS62050, TPS62051 |
|
|
0.02 |
0.1 |
µA |
|
Feedback voltage tolerance |
TPS62050, TPS62051 |
VI = 2.7 V to 10 V, 0 mA < IO < 600 mA |
–3% |
|
3% |
|
|
Fixed output voltage tolerance(1) |
TPS62052 |
VI = 2.7 V to 10 V, 0 mA < IO < 600 mA |
–3% |
|
3% |
|
TPS62054 |
VI = 2.7 V to 10 V, 0 mA < IO < 600 mA |
–3% |
|
3% |
|
TPS62056 |
VI = 3.75 V to 10 V, 0 mA < IO < 600 mA |
–3% |
|
3% |
|
|
Resistance of internal voltage divider for fixed-voltage versions |
|
700 |
1000 |
1300 |
kΩ |
|
Line regulation |
VO = 3.3 V, VI = 5 V to 10 V, IO = 600 mA |
|
5.2 |
|
mV/V |
|
Load regulation |
VI = 7.2 V; IO = 10 mA to 600 mA |
|
0.0045 |
|
%/mA |
η |
Efficiency |
VI = 5 V; VO = 3.3 V; IO = 300 mA |
|
93% |
|
|
VI = 3.6 V; VO = 2.5 V; IO = 200 mA |
|
93% |
|
|
|
Duty cycle range for main switches |
|
|
|
100% |
|
|
Minimum ton time for main switch |
|
|
100 |
|
ns |
|
Shutdown temperature |
|
|
145 |
|
°C |
|
Start-up time |
IO = 200 mA, VI = 5 V, Vo = 3.3 V, Co = 22 µF, L = 10 µH |
|
1 |
|
ms |