The TPS6209x synchronous switched mode converters are based on DCS-Control™ (direct control with seamless transition into power save mode). This is an advanced regulation topology that combines the advantages of hysteretic and voltage mode control.
The DCS-Control™ topology operates in pulse width modulation (PWM) mode for medium to heavy load conditions and in power save mode at light load currents. In PWM, the converter operates with its nominal switching frequency of 2.8 MHz/1.4 MHz having a controlled frequency variation over the input voltage range. As the load current decreases, the converter enters power save mode, reducing the switching frequency and minimizing the IC quiescent current to achieve high efficiency over the entire load current range. DCS-Control™ supports both operation modes (PWM and PFM) using a single building block having a seamless transition from PWM to power save mode without effects on the output voltage. Fixed output voltage versions provide smallest solution size combined with lowest quiescent current. The TPS6209x family offers excellent DC voltage regulation and load transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits.
The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin is pulled low with a shutdown current of typically 0.6 μA. In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal resistor of 200 Ω discharges the output through the VOS pin smoothly. An internal pull-down resistor of 400 kΩ is connected to the EN pin when the EN pin is low. The pulldown resistor is disconnected when the EN pin is high.
To minimize inrush current during start up, the device has an adjustable softstart depending on the capacitor value connected to the SS pin. The device charges the softstart capacitor with a constant current of typically 7.5 µA. The feedback voltage follows this voltage with a fraction of 1.56 until the internal reference voltage of 0.8 V is reached. The softstart operation is completed once the voltage at the softstart capacitor has reached typically 1.25 V. The soft-start time can be calculated using Equation 1. The larger the softstart capacitor the longer the softstart time. The relation between softstart voltage and feedback voltage can be estimated using Equation 2.
During startup, the switch current limit is reduced to 1/3 (~1.5 A) of its typical current limit of 4.6 A. Once the output voltage exceeds typically 0.6 V, the current limit is released to its nominal value. The device provides a reduced load current of ~1.5 A when the output voltage is below typically 0.6 V. Due to this, a small or no softstart time may trigger the short circuit protection during startup especially for larger output capacitors. This is avoided by using a larger softstart capacitance to extend the softstart time. See Short Circuit Protection (Hiccup-Mode) for details of the reduced current limit during startup. Leaving the softstart pin floating sets the minimum start-up time (around 50µs).
The SS pin is externally driven by another voltage source to achieve output voltage tracking. The application circuit is shown in Figure 7. The internal reference voltage follows the voltage at the SS pin with a fraction of 1.56 until the internal reference voltage of 0.8 V is reached. The device achieves ratiometric or coincidental (simultaneous) output tracking, as shown in Figure 8.
The R2 value should be set properly to achieve accurate voltage tracking by taking 7.5 μA soft startup current into account. 1 kΩ or smaller is a sufficient value for R2.
For decreasing the SS pin voltage, the device doesn't sink current from the output when the device is in power save mode. So the resulting decreases of the output voltage may be slower than the SS pin voltage if the load is light. When driving the SS pin with an external voltage, do not exceed the voltage rating of the SS pin which is 7 V.
The device is protected against hard short circuits to GND and over-current events. This is implemented by a two level short circuit protection. During start-up and when the output is shorted to GND the switch current limit is reduced to 1/3 of its typical current limit of 4.6 A. Once the output voltage exceeds typically 0.6 V the current limit is released to its nominal value. The full current limit is implemented as a hiccup current limit. Once the internal current limit is triggered 32 times the device stops switching and starts a new start-up sequence after a typical delay time of 66 µs passed by. The device will go through these cycles until the high current condition is released.
To make sure the device starts up under defined conditions, the output gets discharged via the VOS pin with a typical discharge resistor of 200 Ω whenever the device shuts down. This happens when the device is disabled or if thermal shutdown, undervoltage lockout or short circuit hiccup-mode is triggered.
The power good output is low when the output voltage is below its nominal value. The power good becomes high impedance once the output is within 5% of regulation. The PG pin is an open drain output and is specified to typically sink up to 1 mA. This output requires a pull-up resistor to be monitored properly. The pull-up resistor cannot be connected to any voltage higher than the input voltage of the device. The PG output is low when the device is disabled, in thermal shutdown or UVLO. The PG output can be left floating if unused.
The FREQ pin is a digital logic input which sets the nominal switching frequency. Pulling this pin to GND sets the nominal switching frequency to 2.8 MHz and pulling this pin high sets the nominal switching frequency to 1.4 MHz. Since this pin changes the switching frequency it also changes the on-time during pulse frequency modulation (PFM) mode. At 1.4 MHz the on-time is twice the on-time as operating at 2.8 MHz. This pin has an active pull-down resistor of typically 400 kΩ. For applications where efficiency is of highest importance, a lower switching frequency should be selected. A higher switching frequency allows the use of smaller external components, faster load transient response and lower output voltage ripple when using same L-C values.
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. UVLO shuts down the device at input voltages lower than typically 2.2 V with a 200 mV hysteresis.
The device goes into thermal shutdown once the junction temperature exceeds typically 150°C with a 20°C hysteresis.
At medium to heavy load currents, the device operates with pulse width modulation (PWM) at a nominal switching frequency of 2.8 MHz or 1.4 MHz depending on the setting of the FREQ pin. As the load current decreases, the converter enters the power save mode operation reducing its switching frequency. The device enters power save mode at the boundary to discontinuous conduction mode (DCM).
As the load current decreases, the converter enters power save mode operation. During power save mode, the converter operates with reduced switching frequency maintaining high efficiency. The power save mode is based on a fixed on-time architecture following Equation 3. When operating at 1.4 MHz the on-time is twice as long as the on-time for 2.8 MHz operation. This results in larger output voltage ripple, as shown in Figure 19 and Figure 20, and slightly higher output voltage at no load, as shown in Figure 16 and Figure 17. To have the same output voltage ripple at 1.4 MHz during PFM mode, either the output capacitor or the inductor value needs to be increased. As an example, operating at 2.8 MHz using 0.47 µH inductor gives the same output voltage ripple as operating with 1.4 MHz using 1 µH inductor.
In power save mode the output voltage rises slightly above the nominal output voltage in PWM mode, as shown in Figure 16 and Figure 17. This effect can be reduced by increasing the output capacitance or the inductor value. This effect can also be reduced by programming the output voltage of the TPS62090 lower than the target value. As an example, if the target output voltage is 3.3 V, then the TPS62090 can be programmed to 3.3 V – 0.8%. As a result the output voltage accuracy is now -2.2% to +2.2% instead of -1.4% to 3%. The output voltage accuracy in PFM operation is reflected in the electrical specification table and given for a 22 µF output capacitor.
The device offers low input to output voltage difference by entering 100% duty cycle mode. In this mode the high side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage where the output voltage falls below its nominal regulation value is given by:
RDS(on) = High side FET on-resistance
RL = DC resistance of the inductor