SLVSB35C October   2012  – July 2015 TPS62175 , TPS62177


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Enable/Shutdown (EN)
      2. 8.3.2 Output Discharge
      3. 8.3.3 Current Limit and Short Circuit Protection
      4. 8.3.4 Power Good (PG)
      5. 8.3.5 Undervoltage Lockout (UVLO)
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft Start
      2. 8.4.2 Pulse Width Modulation (PWM) Operation
      3. 8.4.3 Power Save Mode Operation
      4. 8.4.4 Sleep Mode Operation
      5. 8.4.5 100% Mode Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. Programming the Output Voltage
        2. External Component Selection
          1. Output Filter and Loop Stability
          2. Inductor Selection
          3. Output Capacitor Selection
          4. Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Microcontroller Power Supply
      2. 9.3.2 Inverting Power Supply
      3. 9.3.3 TPS62175 Adjustable Output Voltages
        1. 5-V / 0.5-A Power Supply
        2. 2.5-V / 0.5-A Power Supply
        3. 1.8-V / 0.5-A Power Supply
        4. 1.2-V / 0.5-A Power Supply
        5. 1-V / 0.5-A Power Supply
      4. 9.3.4 TPS62177 Fixed 3.3-V / 0.5-A Power Supply
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Information
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQC|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The input capacitor needs to be placed as close as possible to the IC pins (VIN, PGND). The inductor should be placed close to the SW pin and connect directly to the output capacitor - minimizing the loop area between the SW pin, inductor, output capacitor and PGND pin. Also, sensitive nodes like FB and VOS should be connected with short wires, not nearby high dv/dt signals (for example, SW). The feedback resistors, R1 and R2, should be placed close to the IC and connect directly to the AGND and FB pins.

A proper layout is critical for the operation of a switch mode power supply, even more at high switching frequencies. Therefore the PCB layout of the TPS6217x demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. See Figure 62 for the recommended layout of the TPS62175, which is implemented on the EVM. Information can be found in the EVM Users Guide, TPS62175EVM-098 Evaluation Module (SLVU743). Alternatively, the EVM Gerber data are available for download here, SLVC453.

11.2 Layout Example

TPS62175 TPS62177 SLVSAB35_layout.gif Figure 62. Layout Example Recommendation

The exposed thermal pad must be soldered to AGND and on the circuit board for mechanical reliability and to achieve appropriate power dissipation.

11.3 Thermal Information

The TPS6217x is designed for a maximum operating junction temperature (TJ) of 125°C. Therefore the maximum output power is limited by the power losses. Because the thermal resistance of the package is given, the size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To get an improved thermal behavior, TI recommends using top layer metal to connect the device with wide and thick metal lines (see Figure 62). Internal ground layers can connect to vias directly under the IC for improved thermal performance.

For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics Application Note, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017), and Semiconductor and IC Package Thermal Metrics (SPRA953).