SLVSCH9E December   2014  – March 2022 TPS62406-Q1 , TPS62407-Q1 , TPS62422-Q1 , TPS62423-Q1 , TPS62424-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Converter 1
      2. 8.1.2 Converter 2
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable
      2. 8.3.2 DEF_1 Pin Function
      3. 8.3.3 180° Out-of-Phase Operation
      4. 8.3.4 Short-Circuit Protection
      5. 8.3.5 Thermal Shutdown
      6. 8.3.6 EasyScale Interface: One-Pin Serial Interface for Dynamic Output-Voltage Adjustment
        1. 8.3.6.1 General
        2. 8.3.6.2 Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Save Mode
        1. 8.4.1.1 Dynamic Voltage Positioning
        2. 8.4.1.2 Soft Start
        3. 8.4.1.3 100% Duty-Cycle Low-Dropout Operation
        4. 8.4.1.4 Undervoltage Lockout
      2. 8.4.2 Mode Selection
    5. 8.5 Programming
      1. 8.5.1 Addressable Registers
        1. 8.5.1.1 Bit Decoding
        2. 8.5.1.2 Acknowledge
        3. 8.5.1.3 Mode Selection
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting
          1. 9.2.2.1.1 Converter 1 Fixed Default Output-Voltage Setting
          2. 9.2.2.1.2 Converter 2 Fixed Default Output-Voltage Setting
        2. 9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Output-Capacitor Selection
          3. 9.2.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Mode Selection

Use of the MODE/DATA pin for two functions, interface and mode selection, necessitates a determination of when to decode the bit stream or to change the operation mode.

The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level. The device also stays in forced PWM mode during the entire protocol reception time.

With a falling edge on the MODE/DATA pin, the device starts bit decoding. If the MODE/DATA pin stays low for at least ttimeout, the device gets an internal time-out and enables power-save-mode operation.

The device ignores a protocol sent within this time because the first interpretation of a falling edge for the mode change is at the start of the first bit. In this case, TI recommends sending the protocol first, and then changing to power-save mode at the end of the protocol.

GUID-BC550465-756D-4542-A641-BCF0A73F373C-low.gifFigure 8-3 EasyScale Protocol Overview
Table 8-2 EasyScale Bit Description
BYTEBIT NUMBERNAMETRANSMISSION DIRECTIONDESCRIPTION
Device address byte7DA7IN0 MSB device address
6DA6IN1
5DA5IN0
4DA4IN0
4E hex3DA3IN1
2DA2IN1
1DA1IN1
0DA0IN0 LSB device address
Data byte7 (MSB)RFAINRequest for acknowledge; if high, the device applies an acknowledge condition.
6A1Address bit 1
5A0Address bit 0
4D4Data bit 4
3D3Data bit 3
2D2Data bit 2
1D1Data bit 1
0 (LSB)D0Data bit 0
ACKOUTAcknowledge condition active 0, the device applies this condition only in the case of a set RFA bit. Open-drain output, the host must pull the line high with a pullup resistor.
One can only use this feature if the master has an open-drain output stage. In case of a push-pull output stage, do not request an acknowledge condition.
GUID-515AD016-4983-41EA-B7F2-522EB0CF753E-low.gifFigure 8-4 EasyScale Protocol Without Acknowledge
GUID-905C5AF6-EA0A-4E7F-A0CE-EC907C4CE19A-low.gifFigure 8-5 EasyScale Protocol Including Acknowledge
GUID-606D58C4-AC74-4A2F-929D-209CA47A1751-low.gifFigure 8-6 EasyScale – Bit Coding
GUID-D07A8E79-7B7F-4330-A01E-97004B00517B-low.gifFigure 8-7 MODE/DATA PIN: Mode Selection
GUID-4F740278-9A55-4EAD-8AC0-232241D0F9BD-low.gifFigure 8-8 MODE/DATA Pin: Power-Save-Mode and Interface Communication
Table 8-3 Selectable Output Voltages for Converter 1,
With Pin DEF_1 as Digital Input
TPS624xx-Q1 OUTPUT
VOLTAGE [V]
REGISTER REG_DEF_1_LOW
TPS624xx-Q1
VOLTAGE [V]
REGISTER REG_DEF_1_HIGH
D4D3D2D1D0
00.80.900000
10.8250.92500001
20.850.9500010
30.8750.97500011
40.91.000100
50.9251.02500101
60.951.05000110
70.9751.07500111
81.01.101000
91.0251.12501001
101.0501.15001010
111.0751.17501011
121.11.201100
131.1251.22501101
141.1501.2501110
151.1751.27501111
161.21.310000
171.2251.32510001
181.251.35010010
191.2751.37510011
201.31.410100
211.3251.42510101
221.3501.45010110
231.3751.47510111
241.41.511000
251.4251.52511001
261.4501.5511010
271.4751.57511011
281.51.611100
291.5251.711101
301.551.811110
311.5751.911111
Table 8-4 Selectable Output Voltages for Converter 2,
(ADJ2 Connected to VOUT2)
OUTPUT VOLTAGE [V]
FOR REGISTER REG_DEF_2
D4D3D2D1D0
00.600000
10.8500001
20.900010
30.9500011
4100100
51.0500101
61.100110
71.1500111
81.201000
91.2501001
101.301010
111.3501011
121.401100
131.4501101
141.501110
151.5501111
161.610000
171.710001
181.810010
191.8510011
20210100
212.110101
222.210110
232.310111
242.411000
252.511001
262.611010
272.711011
282.811100
292.8511101
30311110
313.311111