SLVSFJ3C May   2022  – October 2023 TPS62870-Q1 , TPS62871-Q1 , TPS62872-Q1 , TPS62873-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Options
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 I2C Interface Timing Characteristics
    7. 8.7 Timing Requirements
    8. 8.8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Fixed-Frequency DCS Control Topology
      2. 9.3.2  Forced PWM and Power Save Modes
      3. 9.3.3  Precise Enable
      4. 9.3.4  Start-Up
      5. 9.3.5  Switching Frequency Selection
      6. 9.3.6  Output Voltage Setting
        1. 9.3.6.1 Output Voltage Range
        2. 9.3.6.2 Output Voltage Setpoint
        3. 9.3.6.3 Non-Default Output Voltage Setpoint
        4. 9.3.6.4 Dynamic Voltage Scaling
      7. 9.3.7  Compensation (COMP)
      8. 9.3.8  Mode Selection and Clock Synchronization (MODE/SYNC)
      9. 9.3.9  Spread Spectrum Clocking (SSC)
      10. 9.3.10 Output Discharge
      11. 9.3.11 Undervoltage Lockout (UVLO)
      12. 9.3.12 Overvoltage Lockout (OVLO)
      13. 9.3.13 Overcurrent Protection
        1. 9.3.13.1 Cycle-by-Cycle Current Limiting
        2. 9.3.13.2 Hiccup Mode
        3. 9.3.13.3 Current Limit Mode
      14. 9.3.14 Power Good (PG)
        1. 9.3.14.1 Standalone or Primary Device Behavior
        2. 9.3.14.2 Secondary Device Behavior
      15. 9.3.15 Remote Sense
      16. 9.3.16 Thermal Warning and Shutdown
      17. 9.3.17 Stacked Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-On Reset
      2. 9.4.2 Undervoltage Lockout
      3. 9.4.3 Standby
      4. 9.4.4 On
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
      2. 9.5.2 Standard, Fast, Fast Mode Plus Protocol
      3. 9.5.3 I2C Update Sequence
      4. 9.5.4 I2C Register Reset
    6. 9.6 Register Map
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting the Inductor
        2. 10.2.2.2 Selecting the Input Capacitors
        3. 10.2.2.3 Selecting the Compensation Resistor
        4. 10.2.2.4 Selecting the Output Capacitors
        5. 10.2.2.5 Selecting the Compensation Capacitor, CC
        6. 10.2.2.6 Selecting the Compensation Capacitor, CC2
      3. 10.2.3 Application Curves
    3. 10.3 Best Design Practices
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.6.2 Output Voltage Setpoint

Together with the selected range, the VSET[7:0] bits in the VSET register control the output voltage setpoint of the device (see Table 9-4).

Table 9-4 Start-Up Voltage Settings
VRANGE[1:0]Output Voltage Setpoint
0b000.4 V + VSET[7:0] × 1.25 mV
0b010.4 V + VSET[7:0] × 2.5 mV
0b100.4 V + VSET[7:0] × 5 mV
0b110.8 V + VSET[7:0] × 10 mV

During initialization, the device reads the state of the VSEL pin and selects the default output voltage according to Table 9-5. Note that the VSEL pin also selects the I2C target address of the device (see Table 9-10).

Table 9-5 Default Output Voltage Setpoints
VSEL Pin(1)Device NumberVSET[7:0]Output Voltage Setpoint
6.2 kΩ to GNDTPS6287x-Q10x5A850 mV
TPS6287xY0-Q10x14500 mV
TPS6287xY1-Q10x50800 mV
TPS6287xY2-Q1

0x64

1800 mV
TPS6287xY3-Q1

0x52

810 mV

TPS6287xY4-Q1

0x5A

850 mV

TPS6287xY5-Q10x1E

1100 mV

TPS6287xY6-Q1

0x28

1200 mV

TPS6287xN0-Q10x14500 mV
TPS6287xN1-Q10x50800 mV
TPS6287xN2-Q1

0x64

1800 mV

TPS6287xN3-Q10x781000 mV
Short Circuit to GND

All, Except TPS6287xx2-Q1, TPS6287xY5-Q1, TPS6287xY6-Q1

0x46750 mV
Short Circuit to GND

TPS6287xx2-Q1, TPS6287xY5-Q1, TPS6287xY6-Q1

0x46

1500 mV

Short Circuit to VINAll, Except TPS6287xx2-Q1

, TPS6287xY5-Q1, TPS6287xY6-Q1

0x5F875 mV
Short Circuit to VINTPS6287xx2-Q1, TPS6287xY5-Q1, TPS6287xY6-Q10x5F

1750 mV

47 kΩ to VINTPS6287x-Q10x781000 mV
TPS6287xY0-Q10x82

1050 mV

TPS6287xY1-Q10x50800 mV
TPS6287xY2-Q1

0xFA

3300 mV

TPS6287xY3-Q1

0x78

1000 mV

TPS6287xY4-Q1

0x5A

850 mV

TPS6287xY5-Q1

0xFA

3300 mV

TPS6287xY6-Q1

0xAA

2500 mV

TPS6287xN0-Q10x821050 mV
TPS6287xN1-Q10x58840 mV
TPS6287xN2-Q1

0xFA

3300 mV

TPS6287xN3-Q10x8C1100 mV
(1) For a reliable voltage setting, ensure there is no stray current path connected to the VSEL pin and that the parasitic capacitance between the VSEL pin and GND is less than 100 pF.

If the user programs new output voltage setpoint (VOUT[7:0]), output voltage range (VRANGE[1:0]), or soft-start time (SSTIME[1:0]) settings when the device has already begun its soft-start sequence, the device ignores the new values until the soft-start sequence is complete. If the user changes the value of VSET[7:0] during soft start, the device first ramps to the value that VSET[7:0] had when the soft-start sequence began. Then, when soft start is complete, ramps up or down to the new value.

If the user changes VOUT[7:0], VRAMP[1:0], or SSTIME[1:0] while EN is low, the device uses the new values the next time the user enables it.

During start-up, the output voltage ramps up to the target value set by the VSEL pin before ramping up or down to any new value programmed to the device over the I2C interface.