SLVSFU1E April   2023  – August 2025 TPS62874-Q1 , TPS62875-Q1 , TPS62876-Q1 , TPS62877-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - Q100
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency DCS-Control Topology
      2. 8.3.2  Forced-PWM and Power-Save Modes
      3. 8.3.3  Transient Non-Synchronous Mode (optional)
      4. 8.3.4  Precise Enable
      5. 8.3.5  Start-Up
      6. 8.3.6  Switching Frequency Selection
      7. 8.3.7  Output Voltage Setting
        1. 8.3.7.1 Output Voltage Range
        2. 8.3.7.2 Output Voltage Setpoint
        3. 8.3.7.3 Non-Default Output Voltage Setpoint
        4. 8.3.7.4 Dynamic Voltage Scaling
        5. 8.3.7.5 Droop Compensation
      8. 8.3.8  Compensation (COMP)
      9. 8.3.9  Mode Selection / Clock Synchronization (MODE/SYNC)
      10. 8.3.10 Spread Spectrum Clocking (SSC)
      11. 8.3.11 Output Discharge
      12. 8.3.12 Undervoltage Lockout (UVLO)
      13. 8.3.13 Overvoltage Lockout (OVLO)
      14. 8.3.14 Overcurrent Protection
        1. 8.3.14.1 Cycle-by-Cycle Current Limiting
        2. 8.3.14.2 Hiccup Mode
        3. 8.3.14.3 Current-Limit Mode
      15. 8.3.15 Power Good (PG)
        1. 8.3.15.1 Standalone, Primary Device Behavior
        2. 8.3.15.2 Secondary Device Behavior
      16. 8.3.16 Remote Sense
      17. 8.3.17 Thermal Warning and Shutdown
      18. 8.3.18 Stacked Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Undervoltage Lockout
      3. 8.4.3 Standby
      4. 8.4.4 On
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
      6. 8.5.6 Dynamic Voltage Scaling (DVS)
  10. 9 Device Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Selecting the Input Capacitors
        3. 10.2.2.3 Selecting the Compensation Resistor
        4. 10.2.2.4 Selecting the Output Capacitors
        5. 10.2.2.5 Selecting the Compensation Capacitor CC
        6. 10.2.2.6 Selecting the Compensation Capacitor CC2
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application Using Two TPS62876-Q1 in a Stacked Configuration
      1. 10.3.1 Design Requirements For Two Stacked Devices
      2. 10.3.2 Detailed Design Procedure
        1. 10.3.2.1 Selecting the Compensation Resistor
        2. 10.3.2.2 Selecting the Output Capacitors
        3. 10.3.2.3 Selecting the Compensation Capacitor CC
      3. 10.3.3 Application Curves for Two Stacked Devices
    4. 10.4 Typical Application Using Three TPS62876-Q1 in a Stacked Configuration
      1. 10.4.1 Design Requirements For Three Stacked Devices
      2. 10.4.2 Detailed Design Procedure
        1. 10.4.2.1 Selecting the Compensation Resistor
        2. 10.4.2.2 Selecting the Output Capacitors
        3. 10.4.2.3 Selecting the Compensation Capacitor CC
      3. 10.4.3 Application Curves for Three Stacked Devices
    5. 10.5 Best Design Practices
    6. 10.6 Power Supply Recommendations
    7. 10.7 Layout
      1. 10.7.1 Layout Guidelines
      2. 10.7.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.7.1 Output Voltage Range

The device has three different voltage ranges. The VRANGE[1:0] bits in the CONTROL1 register control which range is active (see Table 8-4).

Table 8-3 Voltage Ranges
VRANGE[1:0]Voltage Range
0b000.4 V to 0.71875V in 1.25mV steps
0b010.4 V to 1.0375V in 2.5mV steps
0b100.4V to 1.675V in 5mV steps
0b110.4V to 1.675V in 5mV steps

Note that every change to the VRANGE[1:0] bits must be followed by a write to the VSET register – even if the value of the VSET[7:0] bits does not change. This sequence is necessary for the device to start to use the new voltage range.