11 Device Registers

Table 11-1 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 11-1 must be considered as reserved locations and the register contents must not be modified.

Table 11-1 DEVICE Registers

Address	Acronym	Register Name	Section
0h	VSET	Output Voltage Setpoint	Go
1h	CONTROL1	Control 1	Go
2h	CONTROL2	Control 2	Go
3h	CONTROL3	Control 3	Go
4h	STATUS	Status	Go

Complex bit access types are encoded to fit into small table cells. Table 11-2 shows the codes that are used for access types in this section.

Table 11-2 Device Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

11.1 VSET Register (Address = 0h) [Reset = X]

VSET is shown in Figure 11-1 and described in Table 11-3.

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This register controls the output voltage setpoint

Figure 11-1 VSET Register

7	6	5	4	3	2	1	0
VSET
R/W-X

Table 11-3 VSET Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VSET	R/W	X	Output voltage setpoint (see also the range-setting bits in the CONTROL2 register). Range 1: Output voltage setpoint = 0.4 V + VSET[7:0] × 1.25 mV Range 2: Output voltage setpoint = 0.4 V + VSET[7:0] × 2.5 mV Range 3: Output voltage setpoint = 0.4 V + VSET[7:0] × 5 mV The state of the VSEL pin during power up determines the reset value.

11.2 CONTROL1 Register (Address = 1h) [Reset = 2Ah]

CONTROL1 is shown in Figure 11-2 and described in Table 11-4.

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This register controls various device configuration options

Figure 11-2 CONTROL1 Register

7	6	5	4	3	2	1	0
RESET	SSCEN	SWEN	FPWMEN	DISCHEN	HICCUPEN	VRAMP
R/W-0b	R/W-0b	R/W-1b	R/W-0b	R/W-1b	R/W-0b	R/W-10b

Table 11-4 CONTROL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESET	R/W	0b	Reset device. 0b = No effect 1b = The device is powered down, the pin status is read and all registers are reset to their default value. The device is then powered up again starting with a soft-start cycle. Reading this bit always returns 0.
6	SSCEN	R/W	0b	Spread spectrum clocking enable. 0b = SSC operation disabled 1b = SSC operation enabled
5	SWEN	R/W	1b	Software enable. 0b = Switching disabled (register values retained) 1b = Switching enabled (without the enable delay)
4	FPWMEN	R/W	0b	Forced-PWM enable. 0b = Power-save operation enabled 1b = Forced-PWM operation enabled This bit is logically ORed with the MODE/SYNC pin: If a high level or a synchronization clock is applied to the MODE/SYNC pin, the device operates in Forced-PWM, regardless of the state of this bit.
3	DISCHEN	R/W	1b	Output discharge enable. 0b = Output discharge disabled. 1b = Output discharge enabled.
2	HICCUPEN	R/W	0b	Hiccup operation enable. 0b = Hiccup operation disabled 1b = Hiccup operation enabled. Do not enable Hiccup operation during stacked operation
1-0	VRAMP	R/W	10b	Output voltage ramp speed when changing from one output voltage setting to another. 00b = 10 mV/µs 01b = 5 mV/µs 10b = 1.25 mV/µs 11b = 0.5 mV/µs

11.3 CONTROL2 Register (Address = 2h) [Reset = 0Ah]

CONTROL2 is shown in Figure 11-3 and described in Table 11-5.

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This register controls various device configuration options

Figure 11-3 CONTROL2 Register

7	6	5	4	3	2	1	0
RESERVED			SYNC_OUT_PHASE	VRANGE		SSTIME
R/W-000b			R/W-0b	R/W-10b		R/W-10b

Table 11-5 CONTROL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	000b	Reserved for future use. To ensure compatibility with future device variants, program these bits to 0.
4	SYNC_OUT_PHASE	R/W	0b	Phase shift of SYNC_OUT with reference to internal clk or external clk applied at MODE/SYNC. 0b = SYNC_OUT is phase shifted by 120° 1b = SYNC_OUT is phase shifted by 180° The phase relation of 180° is only valid from the primary to the first secondary converter.
3-2	VRANGE	R/W	10b	Output voltage range. 00b = 0.4 V to 0.71875 V in 1.25-mV steps 01b = 0.4 V to 1.0375 V in 2.5-mV steps 10b = 0.4 V to 1.675 V in 5-mV steps 11b = 0.4 V to 1.675 V in 5-mV steps
1-0	SSTIME	R/W	10b	Soft-start ramp time. 00b = 0.5 ms 01b = 0.77 ms 10b = 1 ms 11b = 2 ms

11.4 CONTROL3 Register (Address = 3h) [Reset = 00h]

CONTROL3 is shown in Figure 11-4 and described in Table 11-6.

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This register controls various device configuration options

Figure 11-4 CONTROL3 Register

7	6	5	4	3	2	1	0
RESERVED					DROOPEN	SINGLE	PGBLNKDVS
R/W-00000b					R/W-0b	R/W-0b	R/W-0b

Table 11-6 CONTROL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	00000b	Reserved for future use. To ensure compatibility with future device variants, program these bits to 0.
2	DROOPEN	R/W	0b	Droop compensation enable 0b = droop compensation disabled 1b = droop compensation enabled
1	SINGLE	R/W	0b	Single operation. This bit controls the internal EN pulldown and SYNCOUT functions. 0b = EN pin pulldown and SYNCOUT enabled 1b = EN pin pulldown and SYNCOUT disabled. Do not set during stacked operation
0	PGBLNKDVS	R/W	0b	Power-good blanking during DVS. 0b = PG pin reflects the output of the window comparator 1b = PG pin is high impedance during DVS

11.5 STATUS Register (Address = 4h) [Reset = 00h]

STATUS is shown in Figure 11-5 and described in Table 11-7.

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This register returns the device status flags

Figure 11-5 STATUS Register

7	6	5	4	3	2	1	0
RESERVED		HICCUP	ILIM	TWARN	TSHUT	PBUV	PBOV
R/W-00b		R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b	R/W-0b

Table 11-7 STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	00b	Reserved for future use. To ensure compatibility with future device variants, ignore these bits.
5	HICCUP	R/W	0b	Hiccup. This bit reports whether a hiccup event occurred since the last time the STATUS register was read. 0b = No hiccup event occurred 1b = A hiccup event occurred
4	ILIM	R/W	0b	Current limit. This bit reports whether an current limit event occurred since the last time the STATUS register was read. 0b = No current limit event occurred 1b = An current limit event occurred
3	TWARN	R/W	0b	Thermal warning. This bit reports whether a thermal warning event occurred since the last time the STATUS register was read. 0b = No thermal warning event occurred 1b = A thermal warning event occurred
2	TSHUT	R/W	0b	Thermal shutdown. This bit reports whether a thermal shutdown event occurred since the last time the STATUS register was read. 0b = No thermal shutdown event occurred 1b = A thermal shutdown event occurred
1	PBUV	R/W	0b	Power-bad undervoltage. This bit reports whether a power-bad event (output voltage too low) occurred since the last time the STATUS register was read. 0b = No power-bad undervoltage event occurred 1b = A power-bad undervoltage event occurred
0	PBOV	R/W	0b	Power-bad overvoltage. This bit reports whether a power-bad event (output voltage too high) occurred since the last time the STATUS register was read. 0b = No power-bad overvoltage event occurred 1b = A power-bad overvoltage event occurred