SLVS504B March   2004  – September  2015 TPS65012

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Battery Charger Electrical Characteristics
    7. 6.7 Serial Interface Timing Requirements
    8. 6.8 Dissipation Ratings
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Battery Charger
        1. 7.3.1.1 Autonomous Power Source Selection
        2. 7.3.1.2 Temperature Qualification
        3. 7.3.1.3 Battery Preconditioning
        4. 7.3.1.4 Battery Charge Current
        5. 7.3.1.5 Battery Voltage Regulation
        6. 7.3.1.6 Charge Termination and Recharge
        7. 7.3.1.7 Sleep Mode
        8. 7.3.1.8 PG Output
        9. 7.3.1.9 Thermal Considerations for Setting Charge Current
      2. 7.3.2 Step-Down Converters, VMAIN and VCORE
        1. 7.3.2.1 Power-Save Mode Operation
        2. 7.3.2.2 Forced PWM
        3. 7.3.2.3 Dynamic Voltage Positioning
        4. 7.3.2.4 Soft Start
        5. 7.3.2.5 100% Duty Cycle Low-Dropout Operation
        6. 7.3.2.6 Active Discharge When Disabled
        7. 7.3.2.7 Power-Good Monitoring
        8. 7.3.2.8 Overtemperature Shutdown
      3. 7.3.3 Low-Dropout Voltage Regulators
        1. 7.3.3.1 Power-Good Monitoring
        2. 7.3.3.2 Enable and Sequencing
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Power-Up Sequencing
      6. 7.3.6 System Reset and Control Signals
      7. 7.3.7 Vibrator Driver
    4. 7.4 Device Functional Modes
      1. 7.4.1 TPS65012 Power States Description
        1. 7.4.1.1 State 1: No Power
        2. 7.4.1.2 State 2: ON
        3. 7.4.1.3 State 3: Low-Power Mode
        4. 7.4.1.4 State 4: Shutdown
    5. 7.5 Programming
      1. 7.5.1 LED2 Output
      2. 7.5.2 Interrupt Management
      3. 7.5.3 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1  CHGSTATUS Register (Address: 01h—Reset: 00h)
      2. 7.6.2  REGSTATUS Register (Address: 02h—Reset: 00h)
      3. 7.6.3  MASK1 Register (Address: 03h—Reset: FFh)
      4. 7.6.4  MASK2 Register (Address: 04h—Reset: FFh)
      5. 7.6.5  ACKINT1 Register (Address: 05h—Reset: 00h)
      6. 7.6.6  ACKINT2 Register (Address: 06h—Reset: 00h)
      7. 7.6.7  CHGCONFIG Register Address: 07h—Reset: 1Bh
      8. 7.6.8  LED1_ON Register (Address: 08h—Reset: 00h)
      9. 7.6.9  LED1_PER Register (Address: 09h—Reset: 00h)
      10. 7.6.10 LED2_ON Register (Address: 0Ah—Reset: 00h)
      11. 7.6.11 LED2_PER (Register Address: 0Bh—Reset: 00h)
      12. 7.6.12 VDCDC1 Register (Address: 0Ch—Reset: 72h/73h)
      13. 7.6.13 VDCDC2 Register (Address: 0Dh—Reset: 68h/78h)
      14. 7.6.14 VREGS1Register (Address: 0Eh—Reset: 88h)
      15. 7.6.15 MASK3 Register (Address: 0Fh—Reset: 00h)
      16. 7.6.16 DEFGPIO Register Address: (10h—Reset: 00h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS65012 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Inductor Selection for the Main and the Core Converter
          2. 8.2.1.2.2 Output Capacitor Selection
          3. 8.2.1.2.3 Input Capacitor Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Power Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 LDO1 Output Voltage Adjustment
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGZ Package
48-Pin VQFN
Top View
TPS65012 po_lvs149.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CHARGER SECTION
AC 40 I Charger input voltage from AC adapter. The AC pin can be left open or can be connected to ground if the charger is not used.
AGND2 44 Analog ground connection. All analog ground pins are connected internally on the chip.
ISET 37 I External charge current setting resistor connection for use with AC adapter
NC 27 Connect this pin to GND.
PG 11 O Indicates when a valid power supply is present for the charger (open drain)
Thernal Pad - Connect the thermal pad to GND
TS 38 I Battery temperature sense input
USB 43 I Charger input voltage from USB port. The USB pin can be left open or can be connected to ground if the charger is not used.
VBAT_A 41 I Sense input for the battery voltage. Connect directly with the battery.
VBAT_B 42 O Power output of the battery charger. Connect directly with the battery.
SWITCHING REGULATOR SECTION
AGND3 45 Analog ground connection. All analog ground pins are connected internally on the chip.
L1_A, L1_B 9,10 Switch pin of VMAIN converter. The VMAIN inductor is connected here.
L2 4 Switch pin of VCORE converter. The VCORE inductor is connected here.
PGND1_A, PGND1_B 15,16 Power ground for VMAIN converter
PGND2 46 Power ground for VCORE converter
VCC 6 I Power supply for digital and analog circuitry of MAIN and CORE DC-DC converters. This must be connected to the same voltage supply as VINCORE and VINMAIN. Also supplies serial interface block
VCORE 48 I VCORE feedback voltage sense input, connect directly to VCORE
VINCORE 5 I Input voltage for VCORE step-down converter. This must be connected to the same voltage supply as VINMAIN and VCC.
VINMAIN_A, VINMAIN_B 7,8 I Input voltage for VMAIN step-down converter. This must be connected to the same voltage supply as VINCORE and VCC.
VMAIN 13 I VMAIN feedback voltage sense input, connect directly to VMAIN
LDO REGULATOR SECTION
AGND1 21 Analog ground connection. All analog ground pins are connected internally on the chip.
VFB_LDO1 23 I Feedback input from external resistive divider for LDO1
VINLDO1 22 I Input voltage for LDO1
VINLDO2 19 I Input voltage for LDO2
VLDO1 24 O Output voltage for LDO1
VLDO2 20 O Output and feedback voltage for LDO2
DRIVER SECTION
LED2 2 O LED driver, with blink rate programmable via serial interface
VIB 3 O Vibrator driver, enabled via serial interface
CONTROL AND I2C SECTION
BATT_COVER 39 I Indicates if battery cover is in place
DEFCORE 1 I Input signal indicating default VCORE voltage, 0 = 1.5 V, 1 = 1.6 V
DEFMAIN 12 I Input signal indicating default VMAIN voltage, 0 = 3.0 V, 1 = 3.3 V
GPIO1 26 I/O General-purpose open-drain input/output
GPIO2 25 I/O General-purpose open-drain input/output
GPIO3 18 I/O General-purpose open-drain input/output
GPIO4 17 I/O General-purpose open-drain input/output
HOT_RESET 31 I Push-button reset input used to reboot or wakeup processor via TPS65012
IFLSB 28 I LSB of serial interface address used to distinguish two devices with the same address
INT 35 O Indicates a charge fault or termination, or if any of the regulator outputs are below the lower tolerance level, active low (open drain)
LOW_PWR 36 I Input signal indicating deep sleep mode, VCORE is lowered to predefined value or disabled
MPU_RESET 32 O Open-drain reset output generated by user activated HOT_RESET
PB_ONOFF 47 I Push-button enable pin, also used to wakeup processor from low-power mode
PS_SEQ 14 I Sets power-up/down sequence of step-down converters
PWRFAIL 34 O Open-drain output. Active low when UVLO comparator indicates low VBAT condition or when shutdown is about to occur due to an overtemperature condition or when the battery cover is removed (BATT_COVER has gone low).
RESPWRON 33 O Open-drain system reset output, generated according to the state of the LDO1 output voltage.
SCLK 30 I Serial interface clock line
SDAT 29 I/O Serial interface data/address