SLVS670L June   2006  – May 2018 TPS65023 , TPS65023B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
    7. 6.7  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    8. 6.8  Electrical Characteristics: VDCDC1 Step-Down Converter
    9. 6.9  Electrical Characteristics: VDCDC2 Step-Down Converter
    10. 6.10 Electrical Characteristics: VDCDC3 Step-Down Converter
    11. 6.11 I2C Timing Requirements for TPS65023B
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 7.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 7.3.3  Power Save Mode Operation
      4. 7.3.4  Low Ripple Mode
      5. 7.3.5  Soft-Start
      6. 7.3.6  100% Duty Cycle Low Dropout Operation
      7. 7.3.7  Active Discharge When Disabled
      8. 7.3.8  Power-Good Monitoring
      9. 7.3.9  Low-Dropout Voltage Regulators
      10. 7.3.10 Undervoltage Lockout
      11. 7.3.11 Power-Up Sequencing
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 System Reset + Control Signals
        1. 7.5.1.1 DEFLDO1 and DEFLDO2
        2. 7.5.1.2 Interrupt Management and the INT Pin
      2. 7.5.2 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 VERSION Register Address: 00h (Read Only)
      2. 7.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 7.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
      4. 7.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
      5. 7.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
      6. 7.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
      7. 7.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
      8. 7.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
      9. 7.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Voltage Connection
      2. 8.1.2 Unused Regulators
      3. 8.1.3 Reset Condition of DCDC1
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection for the DC-DC Converters
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Output Voltage Selection
        5. 8.2.2.5 VRTC Output
        6. 8.2.2.6 LDO1 and LDO2
        7. 8.2.2.7 TRESPWRON
        8. 8.2.2.8 VCC Filter
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Requirements for Supply Voltages Below 3.0 V
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RSB|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh

The REG_CTRL register is used to disable or enable the power supplies through the serial interface. The contents of the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO condition resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The REG_CTRL bits are automatically reset to default when the corresponding enable pin is low.

Table 7. REG_CTRL Register

REG_CTRL B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function – – VDCDC1 ENABLE VDCDC2 ENABLE VDCDC3 ENABLE LDO2
ENABLE		 LDO1
ENABLE		 –
Default 1 1 1 1 1 1 1 1
Set by signal – – DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ LDO_ENZ LDO_ENZ –
Default value loaded – – UVLO UVLO UVLO UVLO UVLO –
Read and write – – R/W R/W R/W R/W R/W –
Bit 5 VDCDC1 ENABLE
DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when DCDC1_EN returns high.
Bit 4 VDCDC2 ENABLE
DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when DCDC2_EN returns high.
Bit 3 VDCDC3 ENABLE
DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3 converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when DCDC3_EN returns high.
Bit 2 LDO2 ENABLE
LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high.
Bit 1 LDO1 ENABLE
LDO1 Enable. This bit is logically AND’ed with the state of the LDO1_EN pin to turn on LDO1. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 through the serial interface. The bit is reset to 1 when the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high.