SLVSA48A April   2010  – September 2015 TPS65200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Data Transmission Timing
    7. 6.7 Typical Characteristics
      1. 6.7.1 Switching Charger
      2. 6.7.2 OTG Boost
      3. 6.7.3 LDO
      4. 6.7.4 WLED Boost
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Global State Diagram
      2. 7.3.2 LED Driver Operation
        1. 7.3.2.1 Undervoltage Lockout
        2. 7.3.2.2 Shutdown
        3. 7.3.2.3 Soft-Start Circuit
        4. 7.3.2.4 Open LED Protection
        5. 7.3.2.5 Current Program
        6. 7.3.2.6 Brightness Dimming
        7. 7.3.2.7 Inductor Overcurrent Protection
      3. 7.3.3 HV LDO
      4. 7.3.4 Interrupt Pin
      5. 7.3.5 Current Shunt Monitor
    4. 7.4 Device Functional Modes
      1. 7.4.1 Charge Mode Operation
        1. 7.4.1.1  Input Current Limiting and D+/D- Detection
        2. 7.4.1.2  Bad Adaptor Detection/Rejection (CHBADI)
        3. 7.4.1.3  Input Current Limiting at Start-Up
        4. 7.4.1.4  Charge Profile
        5. 7.4.1.5  Precharge to Fast Charge Threshold (VSHORT)
        6. 7.4.1.6  PWM Controller in Charge Mode
        7. 7.4.1.7  Battery Charging Process
        8. 7.4.1.8  Thermal Regulation and Protection
        9. 7.4.1.9  Safety Timer in Charge and Boost Mode (CH32MI, BST32SI)
        10. 7.4.1.10 Input Voltage Protection in Charge Mode
          1. 7.4.1.10.1 Input Overvoltage Protection (VBUSOVPI)
          2. 7.4.1.10.2 Reverse Current Protection (CHRVPI)
          3. 7.4.1.10.3 Input Voltage Based Dynamic Power Management (CHDPMI)
        11. 7.4.1.11 Battery Protection in Charge Mode
          1. 7.4.1.11.1 Battery Charge Current Limiting
          2. 7.4.1.11.2 Output Overvoltage Protection (CHBATOVPI)
          3. 7.4.1.11.3 Battery Short Protection
        12. 7.4.1.12 Charge Status Output, STAT Pin
      2. 7.4.2 Boost Mode Operation
        1. 7.4.2.1 PWM Controller in Boost Mode
        2. 7.4.2.2 Boost Start Up
        3. 7.4.2.3 PFM Mode at Light Load
        4. 7.4.2.4 Safety Timer in Boost Mode (BST32SI)
        5. 7.4.2.5 Protection in Boost Mode
          1. 7.4.2.5.1 Output Overvoltage Protection (BSTBUSOVI)
          2. 7.4.2.5.2 Output Over-Load Protection (BSTOLI)
          3. 7.4.2.5.3 Battery Voltage Protection (BSTLOWVI, BSTBATOVI)
      3. 7.4.3 High Impedance Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
    6. 7.6 Register Maps
      1. 7.6.1  Control Register (CONTROL)
      2. 7.6.2  Charger Config Register A (CONFIG_A)
      3. 7.6.3  Charger Config Register B (CONFIG_B)
      4. 7.6.4  Charger Config Register C (CONFIG_C)
      5. 7.6.5  Charger Config Register D (CONFIG_D)
      6. 7.6.6  WLED Control Register (WLED)
      7. 7.6.7  Status Register A (STATUS_A)
      8. 7.6.8  Status Register B (STATUS_B)
      9. 7.6.9  Interrupt Register 1 (INT1)
      10. 7.6.10 Interrupt Register 2 (INT2)
      11. 7.6.11 Interrupt Register 3 (INT3)
      12. 7.6.12 Interrupt Mask Register 1 (MASK1)
      13. 7.6.13 Interrupt Mask Register 2 (MASK2)
      14. 7.6.14 Interrupt Mask Register 3 (MASK3)
      15. 7.6.15 Chip ID Register (CHIPID)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and switching frequencies. If the layout is not carefully done, the DCDC converters might show noise problems and duty cycle jitter. The input capacitors on VBUS and PMID pins should be placed as close as possible to the input pins for good input voltage filtering. The inductors should be placed as close as possible to the switch pins to minimize the noise coupling into other circuits. The output capacitors must be placed directly from the inductor (charger buck) or Schottky diode (WLED boost) to GND to minimize the ripple current in these traces. All ground pins must be connected directly to the ground plane as should all passive components with ground connections. Figure 60 and Figure 61 show one example for placement and routing of the critical components on a four-layer PCB. In this example all components are placed on the top layer and all routing is done on the top layer or bottom layer. Layer 2 is a solid ground plane and layer 3 is not used for layout. All IC pin connections are notes as [pin number]. For example, the VSYS pin is referenced as [C6].

  • Place C9 and C10 (VSYS) as close to L2 as possible, with short connections to ground.
  • Place C4 close to the IC. Trace current is low (<1 mA).
  • Place C8 as close to the IC as possible. Maximum trace current is 60 mA.
  • Keep C6 - [E6] trace shielded from SWL node to avoid noise coupling.
  • Place C2 and C3 as close to the IC as possible.Connections for C2 - [A3] and C3 - [A2] must not be in any current path; and, must be kept as short as possible. Traces must connect directly to sense resistor R5.
  • Place L1 as close to the IC as possible. Keep traces between L1, D1 and [F6] short and wide.Maximum trace current is 700 mA.
  • Pins [A1] and [A2] must not be shorted at the IC. Route them separately to R5.
  • Place C12 (PMID) as close to the IC as possible.
  • Place input capacitor C7 (VBUS) as close to the IC as possible.
  • Place C1 close to D1 and keep the trace short and wide.
  • Keep [C1], [C2], [C3] (SWC) to L2 connection shortand wide. Adding vias is OK. Maximum trace current is 2 A.
  • Keep VSYS to L1 connection short and wide. Maximum trace current is 700 mA.

10.2 Layout Example

TPS65200 pcb_top_SLVSA48.gif Figure 60. Layout Example – Top PCB Layer
TPS65200 pcb_bottom_SLVSA48.gif Figure 61. Layout Example – Bottom PCB Layer