5.5.2 FLAG Register
The FLAG register contains a bit for each power rail and GPO to keep track of the enable state of the rails while the system is suspended. The following rules apply to the FLAG register:
- The power-up default value for any flag bit is 0.
- Flag bits are read-only and cannot be written to.
- Upon entering a SUSPEND state, the flag bits are set to same value as their corresponding ENABLE bits. Rails and GPOs enabled in a SUSPEND state have flag bits set to 1, while all other flag bits are set to 0. Flag bits are not updated while in the SUSPEND state or when exiting the SUSPEND state.
- The FLAG register is static in WAIT_PWR_EN and ACTIVE state. The FLAG register reflects the enable state of DCDC1, DCDC2, DCDC3, DCDC4, and LDO1; and, reflects the enable state of GPO1, GPO2, and GPO3 during the last SUSPEND state.
The host processor reads the FLAG register to determine if the system powered up from the OFF or SUSPEND state. In the SUSPEND state, typically the DDR memory is kept in self refresh mode and therefore the DC3_FLG or DC4_FLG bits are set.