SLDS187A October 2018 – December 2019 TPS65216
In OFF mode, the PMIC is completely shut down with the exception of a few circuits to monitor the AC_DET, PWR_EN, and PB input. All power rails are turned off and the registers are reset to their default values. The I2C communication interface is turned off. This is the lowest-power mode of operation. To exit OFF mode VIN_BIAS must exceed the UVLO threshold and one of the following wake-up events must occur:
To enter OFF state, ensure that all power rails are assigned to the sequencer, then pull the PWR_EN pin low. Additionally, if the OFFnPFO bit is set to 1b and the PFI input falls below the power fail threshold the device transitions to the OFF state. If a PGOOD or OTS fault occurs while in the ACTIVE state, TPS65216 will transition to the RESET state.