SBVS128F June   2009  – December 2015 TPS727


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configurations and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Soft Start
      3. 7.3.3 Shutdown
      4. 7.3.4 Dropout Voltage
      5. 7.3.5 Undervoltage Lock-out (UVLO)
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with EN Control
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. Input and Output Capacitor Requirements
        2. Transient Response
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 10.1.2 Power Dissipation
      3. 10.1.3 Package Mounting
    2. 10.2 Layout Example
      1. 10.2.1 DSE EVM Board Layout
      2. 10.2.2 YFF EVM Board Layout
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Device Nomenclature
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|4
  • DSE|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance

To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor must be connected directly to the GND pin of the device. High ESR capacitors may degrade PSRR.

10.1.2 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 3:

Equation 3. TPS727 q_pdiss_bvs128.gif

10.1.3 Package Mounting

Solder pad footprint recommendations and recommended land patterns are attached to the end of this document.

10.2 Layout Example

10.2.1 DSE EVM Board Layout

This section provides the TPS727xxDSEEVM-406 board layout and illustrations.

TPS727 assm_layer_lvu325.gif Figure 36. Top Layer Assembly
TPS727 top_layer_lvu325.gif Figure 37. Top Layer Routing
TPS727 bott_layer_lvu325.gif Figure 38. Bottom Layer Routing
TPS727 bott_assm_lvu325.gif Figure 39. Bottom Layer Assembly

10.2.2 YFF EVM Board Layout

This section provides the TPS727xxYFFEVM-407 board layout and illustrations.

TPS727 top_assm_lvu323.gif Figure 40. Top Layer Assembly
TPS727 top_layer_lvu323.gif Figure 41. Top Layer Routing
TPS727 bott_layer_lvu323.gif Figure 42. Bottom Layer Routing
TPS727 bott_assm_lvu323.gif Figure 43. Bottom Layer Assembly