SBVS099G November   2007  – October 2015 TPS74701

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics: VEN = VIN
    7. 6.7 Typical Characteristics: VEN = VIN = 1.8 V, VOUT = 1.5 V
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Programmable Soft-Start
      2. 7.3.2 Enable and Shutdown
      3. 7.3.3 Power Good
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input, Output, and Bias Capacitor Requirements
      2. 8.1.2 Transient Response
      3. 8.1.3 Dropout Voltage
      4. 8.1.4 Sequencing Requirements
      5. 8.1.5 Output Noise
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
    4. 10.4 Estimating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

At TJ = –40°C to 125°C, unless otherwise noted. All voltages are with respect to GND.(1)
MIN MAX UNIT
VIN, VBIAS Input voltage –0.3 6 V
VEN Enable voltage –0.3 6 V
VPG Power good voltage –0.3 6 V
IPG PG sink current 0 1.5 mA
VSS Soft-start voltage –0.3 6 V
VFB Feedback voltage –0.3 6 V
VOUT Output voltage –0.3 VIN + 0.3 V
IOUT Maximum output current Internally limited
Output short-circuit duration Indefinite
PDISS Continuous total power dissipation See Thermal Information
TJ Operating junction temperature –40 125 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input supply voltage VOUT + VDO (VIN) VOUT + 0.3 5.5 V
VEN Enable supply voltage 0 VIN 5.5 V
VBIAS(1) BIAS supply voltage VOUT + VDO (VBIAS)(2) VOUT + 1.4(2) 5.5 V
VOUT Output voltage 0.8 3.3 V
IOUT Output current 0 500 mA
COUT Output capacitor 2.2 µF
CIN Input capacitor(3) 1 µF
CBIAS Bias capacitor 0.1 1 µF
TJ Operating junction temperature –40 125 °C
(1) BIAS supply is required when VIN is below VOUT + 1.62 V.
(2) VBIAS has a minimum voltage of 2.7 V or VOUT + VDO (VBIAS), whichever is higher.
(3) If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF.

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS74701 UNIT
DRC (VSON)(3)
10 PINS
RθJA Junction-to-ambient thermal resistance 41.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 78 °C/W
RθJB Junction-to-board thermal resistance N/A °C/W
ψJT Junction-to-top characterization parameter 0.7 °C/W
ψJB Junction-to-board characterization parameter 11.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRC package are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
  1. The exposed pad is connected to the PCB ground layer through a 3×2 thermal via array.
  2. The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
  3. This data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inches × 3-inches copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections.

6.5 Electrical Characteristics

At VEN = 1.1 V, VIN = VOUT + 0.3V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5 V, and TJ = –40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range VOUT + VDO 5.5 V
VBIAS Bias pin voltage range 2.7 5.5 V
VREF Internal reference (Adjustable) TJ = 25°C 0.796 0.8 0.804 V
VOUT Output voltage range VIN = 5 V, IOUT = 500 mA VREF 3.6 V
Accuracy(1) 2.97 V ≤ VBIAS ≤ 5.5 V,
50 mA ≤ IOUT ≤ 500 mA
–2% ±0.5% 2%
VOUT/VIN Line regulation VOUT (NOM) + 0.3 ≤ VIN  ≤ 5.5 V 0.03 %/V
VOUT/IOUT Load regulation 50 mA ≤ IOUT ≤ 500 mA 0.09 %/A
VDO VIN dropout voltage(2) IOUT = 500 mA,
VBIAS – VOUT (NOM) ≥ 1.62 V(3)
50 120 mV
VBIAS dropout voltage(2) IOUT = 500 mA, VIN = VBIAS 1.31 1.39 V
ICL Current limit VOUT = 80% × VOUT (NOM) 800 1350 mA
IBIAS Bias pin current 1 2 mA
ISHDN Shutdown supply current (IGND) VEN ≤ 0.4 V 1 50 μA
IFB Feedback pin current –1 0.150 1 μA
PSRR Power-supply rejection
(VIN to VOUT)
1 kHz, IOUT = 500 mA,
VIN = 1.8 V, VOUT = 1.5 V
60 dB
300 kHz, IOUT = 500 mA,
VIN = 1.8 V, VOUT = 1.5 V
30
Power-supply rejection
(VBIAS to VOUT)
1 kHz, IOUT = 500 mA,
VIN = 1.8 V, VOUT = 1.5 V
50 dB
300 kHz, IOUT = 500 mA,
VIN = 1.8 V, VOUT = 1.5 V
30
Noise Output noise voltage 100 Hz to 100 kHz,
IOUT = 500 mA, CSS = 0.001 μF
25 × VOUT μVRMS
tSTR Minimum start-up time RLOAD for IOUT = 1 A, CSS = open 200 μs
ISS Soft-start charging current VSS = 0.4 V 440 nA
VEN, HI Enable input high level 1.1 5.5 V
VEN, LO Enable input low level 0 0.4 V
VEN, HYS Enable pin hysteresis 50 mV
VEN, DG Enable pin deglitch time 20 μs
IEN Enable pin current VEN = 5 V 0.1 1 μA
VIT PG trip threshold VOUT decreasing 85 90 94 %VOUT
VHYS PG trip hysteresis 3 %VOUT
VPG, LO PG output low voltage IPG = 1 mA (sinking), VOUT < VIT 0.3 V
IPG, LKG PG leakage current VPG = 5.25 V, VOUT > VIT 0.1 1 μA
TJ Operating junction temperature –40 125 °C
TSD Thermal shutdown temperature Shutdown, temperature increasing 165 °C
Reset, temperature decreasing 140
(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.
(2) Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% less than nominal.
(3) 1.62 V is a test condition of this device and can be adjusted by referring to Figure 6.

6.6 Typical Characteristics: VEN = VIN

At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted.
TPS74701 tc_vin_reg_bvs099.gif
Figure 1. VIN Line Regulation
TPS74701 tc_load_reg_ma_bvs099.gif
Figure 3. Load Regulation
TPS74701 tc_vdo-io_tmp_bvs099.gif
Figure 5. Dropout Voltage vs IOUT and Temperature (TJ)
TPS74701 tc_vb_vdo-io_tmp_tj_bvs099.gif
Figure 7. VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
TPS74701 tc_vin-frq_bvs099.gif
Figure 9. VIN PSRR vs Frequency
TPS74701 tc_noise_dens_bvs099.gif
Figure 11. Noise Spectral Density
TPS74701 tc_bias-vb_tmp_bvs099.gif
Figure 13. BIAS Pin Current vs VBIAS and Temperature (TJ)
TPS74701 tc_lopg-pg_cur_bvs099.gif
Figure 15. Low-Level PG Voltage vs Current
TPS74701 tc_vbias_reg_bvs099.gif
Figure 2. VBIAS Line Regulation
TPS74701 tc_load_reg_bvs099.gif
Figure 4. Load Regulation
TPS74701 tc_vi_drop-vb_bvs099.gif
Figure 6. Dropout Voltage vs (VBIAS – VOUT) and Temperature (TJ)
TPS74701 tc_vbias-frq_bvs099.gif
Figure 8. VBIAS PSRR vs Frequency
TPS74701 tc_psrr-vivo_bvs099.gif
Figure 10. VIN PSRR vs (VIN – VOUT)
TPS74701 tc_bias-io_tmp_bvs099.gif
Figure 12. BIAS Pin Current vs IOUT and Temperature (TJ)
TPS74701 tc_iss-tmp_tj_bvs099.gif
Figure 14. Soft-Start Charging Current (ISS) vs Temperature (TJ)
TPS74701 tc_cur-vbias_vo_bvs099.gif
Figure 16. Current Limit vs (VBIAS – VOUT)

6.7 Typical Characteristics: VEN = VIN = 1.8 V, VOUT = 1.5 V

At TJ = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN = 1.8 V, VOUT = 1.5 V, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted.
TPS74701 tc_vbias-trans_bvs099.gif
Figure 17. VBIAS Line Transient
TPS74701 tc_out_load_trans_bvs099.gif
Figure 19. Output Load Transient Response
TPS74701 tc_pwr_up_dwn_bvs099.gif
Figure 21. Power Up and Power Down
TPS74701 tc_vin-trans_bvs099.gif
Figure 18. VIN Line Transient
TPS74701 tc_turn_on_bvs099.gif
Figure 20. Turnon Response