SLVSAD1B June   2010  – January 2016 TPS80010

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable
      2. 7.3.2 Buck DC-DC Converter and Load Switch
      3. 7.3.3 Boost DC-DC Converter and Post-Regulation LDO
      4. 7.3.4 Battery Monitoring Switch and False Load
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Buck Output Filter Design
        2. 8.2.2.2 Buck Inductor Selection
        3. 8.2.2.3 Buck Output Capacitor Selection
        4. 8.2.2.4 Buck Input Capacitor Selection
        5. 8.2.2.5 Boost Inductor Selection
        6. 8.2.2.6 Boost Input Capacitor
        7. 8.2.2.7 Boost Output Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage (all pins) –0.3 3.6 V
VO Output voltage (all pins) –0.3 3.6 V
TJ Junction temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

MAX UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

TA = 0°C to 85°C; typical values are at TA = 25°C
MIN NOM MAX UNIT
VBAT Input voltage, VIN BOOST, VIN_BUCK, PP_BAT pins 1.95 3.6 V
VIO (IN_VIO) Digital I/O operating voltage 1.8 VBAT V
TA Ambient temperature 0 25 85 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS80010 UNIT
RSM (VQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 37.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.8 °C/W
RθJB Junction-to-board thermal resistance 8.2 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 8.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TA = 0°C to 85°C; typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IQ Quiescent current VBAT = 3 V, all modules enabled 51 μA
IOFF Off current VBAT = 3 V 1 μA
DIGITAL I/O
RPULLDOWN Internal pulldown resistor EN_BOOST, EN_LDO, EN_SW1, EN_BAT_CHECK, EN_BAT_FALSELOAD 157 275 383 kΩ
VIH Input logic-high voltage EN_BOOST, EN_LDO, EN_SW1, EN_BAT_CHECK, EN_BAT_FALSELOAD 0.7 × VIO V
EN_BUCK, BUCK_MODE 0.7 × VBAT
VIL Input logic-low voltage EN_BOOST, EN_LDO, EN_SW1, EN_BAT_CHECK, EN_BAT_FALSELOAD 0.3 × VIO V
EN_BUCK, BUCK_MODE 0.7 × VBAT
VOH Output logic-high voltage PG VIO – 0.2 V
VOL Output logic-low voltage PG 0.2 V
IL_DIG Logic-output load current 1 mA
BUCK CONVERTER
VIN Input voltage at VIN_BUCK 1.95 3.6 V
IO Output current 100 mA
VFB Feedback voltage (output accuracy) PWM, IO = 0 mA to 100 mA,
VIN ≥ 1.85 V to 3.6 V, VBUCK = 1.8 V		 –1.5% 1.5%
PFM 1
VBUCK Buck output voltage 1.8 V
ISW Switch current limit 0.56 0.7 0.84 A
IRUSH Inrush current VIN = 2 V 150 mA
Line regulation PWM, IO = 100 mA 0.9%
PFM, IO = 100 mA 0.9%
Load regulation PWM, VIN = 2.4 V, IO = 0 mA to 100 mA –0.5%
PFM, VIN = 2.4 V, IO = 0 mA to 100 mA 0.5%
Efficiency PFM , IO = 100 mA, VIN = 2.4 V, VBUCK = 1.8 V 92%
PWM, IO = 100 mA, VIN = 2.4 V, VBUCK = 1.8 V 90%
IQ Quiescent current PFM, IO = 0 mA, no switching 21 μA
PFM, IO = 0 mA, switching 25
PWM, IO = 0 mA 5 mA
Shutdown current 0.005 0.15 μA
Leakage current into SW_BUCK 0.01 1 μA
RREC Rectifier on-resistance VGS = 3.6 V 185 380 mΩ
RMAIN Main SW on-resistance VGS = 3.6 V 240 480 mΩ
ΔVLN Line transient output variation PFM, IO = 50 mA, VIN = 2 V → 3.6 V, Δt = 25 µs 10 20 mV
ΔVLD Load transient output variation PFM, VIN = 2.4 V, VBUCK = 1.8 V,
IO = 1 mA → 100 mA, Δt = 1 µs		 30 40 mV
VRIP Output ripple PWM, IO = 100 mA, VIN = 2.4 V 1 10 mVpp
PFM, IO = 10 mA, VIN = 3.6 V 10 20
fSW Switching frequency 2 2.25 2.5 MHz
UVLO Undervoltage lockout threshold 1.7 V
CL Load capacitance 10 μF
L Inductor 2.2 μH
LOAD SWITCH
RON Switch on-resistance VGS = 1.8 V 80 120 mΩ
Maximum load current 360 mA
Turnon inrush current 100 mA
IOFF Off-state current Switch turned off, IO = 0 mA 1 μA
POWER GOOD RESET
VTHRESH Power good threshold voltage 1.68 1.7 1.72 V
VHYS Power good hysteresis 10 15 mV
BOOST CONVERTER
VIN Input voltage at VIN_BOOST Boost mode 1.8 3.1 V
VIN > VBOOST mode, VBOOST = VIN 3.1 3.6
VBOOST Output voltage TA = 0°C–50°C, VIN = 1.8 V to 3.1 V,
IO = 0 mA to 50 mA 		3 3.1 3.2 V
IO Output current VIN = 1.8 V to 3.6 V 50 mA
ISW Switch current limit 200 350 475 mA
IRUSH Inrush current VIN = 2 V 150 mA
RREC Rectifier on-resistance VBOOST = 3.1 V 1 Ω
RMAIN Main SW on-resistance 1 Ω
Line regulation VIN = 2 V to 3 V, IO = 50 mA 0.5%
Load regulation VIN = 2 V, IO = 0–50 mA 0.5%
Boost efficiency VIN = 2.4 V, IO = 5 mA 91%
fSW Oscillator frequency VIN = 2.4 V, IO = 50 mA 91 kHz
625
IQ Quiescent current From VIN supply, IO = 0 mA, VIN = 1.8 V,
VBOOST = 3.1 V		 1 2.5 μA
From VBOOST, IO = 0 mA, VIN = 1.8 V,
VBOOST = 3.1 V		 4 6.5
Shutdown current 0.1 1
Leakage current into SW_BOOST 0.1 1
VUVLO VIN decreasing 0.5 0.7 V
ΔVLN Line transient output variation IO = 10 mA, VIN = 1.8 V → VBOOST, ΔT = 25 µs 10 mV
ΔVLD Load transient output variation VIN = 2.4 V, VBOOST = 3.1 V, IO = 1 mA → 50 mA,
Δt = 1 µs		 5 10 mV
VRIP Output ripple VIN = 1.8 V, IO = 50 mA 4 10 mVpp
IOFF Off-mode current 0.1 1 μA
CL Load capacitance 6 10 22 μF
L Inductance 10 μH
POST REGULATION LDO
VIN Input voltage at IN_VM 3.1 3.6 V
VLDO Output voltage 10 µA ≤ IO ≤ IOMAX 2.91 3 3.09 V
IO Output current Normal mode 50 mA
ILIMIT Current limit VLDO > 1 V 300 400 500 mA
ISHORT Short circuit current Output shorted to ground 30 60 150 mA
VREG Line regulation dVLDO/dVIN at IO = Max 0.2%
LREG Load regulation VLDO (IOMIN) – VLDO(IOMAX) 40 mV
ΔVLN Load transient response IO = 20 mA/µs, VIN = 3.1 V 50 100 mV
IQ Quiescent current IO = 0 mA 16 17.6 µA
PSRR Power-supply ripple rejection f = 120 Hz to 1 kHz at IO = IOMAX/2, VIN = 3.1 V 40 dB
VRIP_NORM Output ripple VBAT < 3.1 V, IO = 50 mA, VIN = VBOOST 0.1 1 mVpp
VRIP_HIBAT Output ripple VBAT > 3.1 V, IO = 50 mA, VIN = VBOOST 4 10 mVpp
Boost plus LDO efficiency VBAT = 2.4 V, IO = 5 mA, VIN = VBOOST 87%
VBAT = 2.4 V, IO = 50 mA, VIN = VBOOST 88%
CL Load capacitance Ceramic capacitor, ESR = 10 mΩ to 150 mΩ 4.7 10 22 µF
BATTERY LOAD MONITOR
VOP Operating voltage 1.8 3.6 V
VIN Input voltage at PP_BAT 1.8 3.6 V
VOUT Output voltage at BAT_CHECK VIN V
ILOAD Load current 10 mA
RON Switch on-resistance VIN = 1.8 V to 3.6 V 12 15 Ω
BATTERY LOAD SWITCH
VOP Operating voltage 1.8 3.6 V
VIN Input voltage at BAT_FALSELOAD 3.6 V
IIN Input current 240 360 mA
RON Switch on-resistance 500 mΩ

6.6 Timing Requirements

MIN NOM MAX UNIT
BUCK CONVERTER
tSTART Start-up time 10 ms
LOAD SWITCH
Output rise time; 10%–90% of final VO, CL = 100 µF 2 4 ms
tON Turnon time; CL = 100 µF 6 ms
tOFF Turnoff time; CL = 100 µF 10 ms
POWER GOOD RESET
ΔtPG Power good time-out delay 100 150 200 ms
BOOST CONVERTER
tSTART Start-up time; from enable, VBOOST = 10% → 90% 0.25 10 ms
POST REGULATION LDO
tON Turn-on time; IO = 0 mA, VLDO = 90%, CL = 2.9 µF 130 500 µs
tOFF Turn-off time; IO = 0 mA, VLDO < 0.5 V, CL = 2.9 µF 3.9 5 ms

6.7 Typical Characteristics

TPS80010 eff_load_lvsad1.gif Figure 1. Buck Efficiency, MODE_BUCK = 0
TPS80010 Vbuck2_load_lvsad1.gif Figure 3. Buck Output Voltage vs Load, MODE_BUCK = 1
TPS80010 vripp_PFM_lvsad1.gif Figure 5. Buck Output-Voltage Ripple, PFM
TPS80010 boost_vo_ripp_lvsad1.gif Figure 7. Boost Output Voltage Ripple
TPS80010 boost_swt_lvsad1.gif Figure 9. Boost Switching Waveform,
Continuous-Current Mode
TPS80010 Vbuck_load_lvsad1.gif Figure 2. Buck Output Voltage vs Load, MODE_BUCK = 0
TPS80010 vripp_PWM_lvsad1.gif Figure 4. Buck Output-Voltage Ripple, PWM
TPS80010 eff_LDO_lvsad1.gif Figure 6. Boost With LDO Efficiency
TPS80010 boost2_vo_ripp_lvsad1.gif Figure 8. Boost Output Voltage Ripple
TPS80010 boost_2_swt_lvsad1.png Figure 10. Boost Switching Waveform,
Discontinuous-Current Mode