SLUSBP5E March   2014  – July 2018 TPS92601-Q1 , TPS92602-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1. 3.1 Typical Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope-Compensation Output Current
      3. 7.3.3 Boost-Current Limit
      4. 7.3.4 Oscillator and PLL
      5. 7.3.5 Control Loop Compensation
      6. 7.3.6 LED Open-Circuit Detection
      7. 7.3.7 Output Short-Circuit and Overcurrent Detection
      8. 7.3.8 Measuring LED Current During a Non-Failure Condition
      9. 7.3.9 LED Dimming Options
        1. 7.3.9.1 Analog Dimming
        2. 7.3.9.2 PWM Dimming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage and Overvoltage Shutdown
      2. 7.4.2 Overtemperature Shutdown
      3. 7.4.3 Device State Diagram
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Boost Regulator With Separate or Paralleled Channels
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency
          2. 8.2.1.2.2  Maximum Output-Current Set Point
          3. 8.2.1.2.3  Output Overvoltage-Protection Set Point
          4. 8.2.1.2.4  Duty Cycle Estimation
          5. 8.2.1.2.5  Inductor Selection
          6. 8.2.1.2.6  Rectifier Diode Selection
          7. 8.2.1.2.7  Output Capacitor Selection
          8. 8.2.1.2.8  Input Capacitor Selection
          9. 8.2.1.2.9  Current Sense and Current Limit
          10. 8.2.1.2.10 Switching MOSFET Selection
          11. 8.2.1.2.11 Loop Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Boost-to-Battery Regulator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Switching Frequency
          2. 8.2.2.2.2  Maximum Output-Current Set Point
          3. 8.2.2.2.3  Output Overvoltage-Protection Set Point
          4. 8.2.2.2.4  Duty Cycle Estimation
          5. 8.2.2.2.5  Inductor Selection
          6. 8.2.2.2.6  Rectifier Diode Selection
          7. 8.2.2.2.7  Output Capacitor Selection
          8. 8.2.2.2.8  Input Capacitor Selection
          9. 8.2.2.2.9  Current Sense and Current Limit
          10. 8.2.2.2.10 Switching MOSFET Selection
          11. 8.2.2.2.11 Loop Compensation
        3. 8.2.2.3 TPS92602y-Q1 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VVDD = 12 VDC, over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
V(VIN_norm) Input voltage range Normal mode after initial start-up, VIN rising 6 40 V
V(VIN_crank) Normal mode after initial start-up, VIN falling 4 40
V(UVLO) Undervoltage lockout PWM1 = PWM2 = High, VIN falling,f(PWMOx) < V(VOUTx) – 2 V 3.72 4 V
V(UVsh) Undervoltage shutdown PWM1 = PWM2 = High, VIN falling, quiescent current < 2 µA 2.8 3.5 V
V(OVSH) Overvoltage shutdown PWM1 = PWM2 = High, VIN falling, V(PWMOx) = V(VOUTx), V(GRDVx) = 0 40 40.7 V
SUPPLY CURRENT
I(stby) Shutdown current VIN = 12 V, PWMIN1 and PWMIN2 = low for > t(CH_OFF),
TA = 25°C		 2 µA
VIN = 12 V, PWMIN1 and PWMIN2 = low for > t(CH_OFF),
TA = 125°C		 3
t(CH_OFF) Channel OFF timer PWMINx = low 9.5 14 18 ms
t(CH_ON) Channel ON timer PWMINx = high, VCC = 5.5 V 1 ms
Inom Normal-mode current in OVP loop VIN = 12 V, PWMINx = high 8 12 mA
GATE DRIVER SUPPLY VCC
V(VCC) Output voltage VIN > 6 V 5.5 6.6 7.4 V
V(VCC_dr) Drop-out voltage 4 V < VIN < 8 V, I(VCC) < 50 mA 400 mV
C(VCC) VCC buffer capacitance 2.2 10 20 µF
I(VCC) Output current (only for internal usage) 80 mA
I(VCC_LIM) Current limit VCC shorted to ground 150 220 mA
GATE DRIVER – LOW-SIDE BOOST NMOS-FET
VGS(NMOS) NMOS gate-source voltage Gate-source voltage to switch on boost NMOS FET. Depends on VCC 5.5 6.6 7.4 V
D(MAX) Maximum duty cycle 93.8%
tr(NMOS) Gate driver rising VCC = 6.6 V, no load 22 ns
tf(NMOS) Gate driver falling VCC = 6 V, no load 8.5 ns
rDS(on)(Source,Nmos) Gate driver resistance, sourcing VCC = 6.6 V, 100-mA load 2.5 4 Ω
rDS(on)(Sink,Nmos) Gate driver resistance, sinking VCC = 6.6 V, 100-mA load 2.5 4 Ω
CURRENT LIMIT – NMOS FET
V(ISNSx) Voltage limit threshold across sense-current resistor 83 100 115 mV
t(ISNSx) Leading edge blanking 200 ns
I(ISNSx) Current on ISNSx  40 50 65  µA
A(PS) VC current-mode gain (ΔVvc / ΔVsns) 4 V/V
GATE DRIVER – HIGH-SIDE PWM PMOS-FET
I(PWMOx_Source) Peak source current V(OUT) – V(PWMOx) = 6.5 V, V(OUT) = 40 V 150 mA
I(PWMOx_Sink) Peak sink current V(OUT) – V(PWMOx) = 0 V, V(OUT) = 40 V 10 mA
V(PWMOx) Output voltage 4 75 V
VGS(PMOS) PMOS gate-source voltage PWMx = high, V(OUT) = 40 V 6 6.9 8 V
VGS(NMOS) NMOS gate-source voltage Sufficient gate-source voltage to switch on the NMOS FET; this depends on VCC. 5.5 6.6 7.4 V
tr(PMOS) HS gate driver rising No load  1 µs
tf(PMOS) HS gate driver falling No load  3 µs
PWM DIMMING
f(PWMIN) Dimming frequency See PWM dimming section 0.2 2 kHz
V(thLOW) Logic low Switch off PMOS dimming FET (low below)  0.8 V
V(thHIGH) Logic high Switch on PMOS dimming FET (high above)  2 V
R(PWMIN_pd) Pulldown resistance at PWMINx pin 90 120 150 kΩ
PWMIN to LED turnoff time 80 ns
PWMIN to LED turnon time 60 ns
INTERNAL PLL OSCILLATOR
f(OSC) Oscillator range 100 600 kHz
Δf(OSC) Oscillator accuracy RT: 20-kΩ resistor. See Equation 2 and Figure 3 for f(OSC) vs RT –20% 20%
f(EXT) Ext. synchronization 100 600 kHz
t(CLKpw) Minimum clock input pulse duration 70  ns
V(RTthLO) RT low voltage 0.8 V
V(RTthHI) RT high voltage 2 V
t(RTdelay) RT rising edge to GDRV1 rising edge 35 ns
t(PLLlock) PLL lock-in time 200  µs
HIGH-SIDE CURRENT-SENSE ERROR AMPLIFIER VFBx < 2.1 V
V(SPSN,Com) Common-mode voltage ISPx, ISNx 4 74 V
V(SPSN_Diff) Full-scale sense voltage ISPx – ISNx 4 V < V(SPSN_Com) < 75 V, VFBx < 2.1 V, TPS92601-Q1, TPS92602-Q1,TPS92601B-Q1, TPS92602B-Q1 150 mV
4 V < V(SPSN_Com) < 75 V, VFBx < 2.1 V, TPS92601A-Q1, TPS92602A-Q1 300
V(SPSN_AC) Sense-voltage accuracy Common-mode voltage 4 V to 75 V –6  6 mV
I(BIAS_SPSN) Input bias current ISPx, ISNx 4 V < V(SPSN_Com) < 75 V, V(SPSN_Diff) = 150 mV 40 µA
I(offset_SPSN) Input offset current ISPx, ISNx TPS92601-1, TPS92602-Q1, TPS92601B-Q1, TPS92602B-Q1, 4 V < V(SPSN_Com) < 75 V, V(SPSN_Diff) = 150 mV 100  135 µA
TPS92601A-Q1, TPS92602A-Q1, 4 V < V(SPSN_Com) < 75 V, V(SPSN_Diff) = 300 mV 175 200
gMC Forward transconductance 1 mS
A(HSCS) HS current-sense gain TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1, TPS92602B-Q1 5 V/V
TPS92601A-Q1, TPS92602A-Q1 2.5 V/V
CURRENT CONTROL ICTRL – ANALOG DIMMING FOR ALL PARAMETERS: VFBx < 2.1 V
I(DIM_LIN) Linear analog dimming range 10% 100%
K(DIMfactor) Dimming factor, V(ICTRL) / V(SNSPx) TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1, TPS92602B-Q1, TA = 25ºC(1) 9.7 10 10.3
TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1, TPS92602B-Q1, TA = 125ºC(1) 9.5 10 10.5
TPS92601A-Q1, TPS92602A-Q1, TA = 25ºC(1) 4.85 5 5.15
TPS92601A-Q1, TPS92602A-Q1, TA = 125ºC(1) 4.75 5 5.25
V(ICTRLx) Adjustable voltage range See Figure 12 0 1.5 V
R(ICTRLpd) Pulldown resistance at ICTRLx pin 0.75 1  1.2 MΩ
ERROR AMPLIFIER - REFERENCE VOLTAGE
V(VFB) Voltage feedback 2.2 V
ΔV(VFB) Voltage FB accuracy –5% 5%
I(BIAS) Input bias current VFB = 2.2 V 500  nA
g(Mv) Forward transconductance 1 mS
INTERNAL SOFT-START
t(softstart) Soft-start time, internal soft-start COMP 0 V to 1.5 V 3.5  ms
DIAGNOSIS – DIAGx PIN
V(OPLED) Open LED failure TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1, TPS92602B-Q1 10 mV
TPS92601A-Q1, TPS92602A-Q1 20
V(DIAG_OP) Low-level voltage, DIAGx pin DIAGx pin pulled low, I(DIAGx) = 100 µA 0.15 V
V(SHLED) Shorted LED failure TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1, TPS92602B-Q1 225 mV
TPS92601A-Q1, TPS92602A-Q1 450
V(DIAG_SH) High-level voltage, DIAGx pin DIAGx pin pulled high, I(DIAGx) = 100 µA 3 3.47 V
V(ILED1) Range for tracking LED current on DIAGx pin Voltage range on DIAGx pin (VIN > 6 V) 0.2 2.85 V
V(ILED2) 0.2 2.85
V(DIAG_AC) Offset of DIAG output buffer At input of DIAG buffer –12 12 mV
K(DIAG_factor) Factor V(DIAG) / V(SPSN) Within linear analog dimming range and DIAG tracking range. Exclusive offset V(DIAG_AC), TPS92601-Q1, TPS92602-Q1, TPS92601B-Q1, TPS92602B-Q1 12.5
Within linear analog dimming range and DIAG tracking range. Exclusive offset V(DIAG_AC), TPS92601A-Q1, TPS92602A-Q1 6.25
COMPENSATION NETWORK – COMPx PIN
V(COMPx) Compensation-network output-pin voltage 0 3.3 V
THERMAL SHUTDOWN
T(SD) Thermal shutdown 165 °C
T(HYS) Hysteresis 20 °C
(1) Within linear analog dimming range (10%–100%). Exclusive offset V(SPSN_AC) = 6 mV