SLVSH65A February   2023  – November 2023 TPSM63610E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Precision Enable and Input Voltage UVLO (EN)
      7. 8.3.7  Frequency Synchronization (SYNC/MODE)
      8. 8.3.8  Spread Spectrum
      9. 8.3.9  Power-Good Monitor (PG)
      10. 8.3.10 Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
      11. 8.3.11 Bias Supply Regulator (VCC, VLDOIN)
      12. 8.3.12 Overcurrent Protection (OCP)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High-Efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Inverting Buck-Boost Regulator with Negative Output Voltage
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Output Voltage Setpoint
          2. 9.2.2.2.2 IBB Maximum Output Current
          3. 9.2.2.2.3 Switching Frequency Selection
          4. 9.2.2.2.4 Input Capacitor Selection
          5. 9.2.2.2.5 Output Capacitor Selection
          6. 9.2.2.2.6 Other Considerations
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -55°C to +125°C, unless otherwise noted. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12. VIN1 shorted to VIN2 = VIN. VOUT is output set point.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN Minimum operating input voltage Needed to start up 3.7 V
Once Operating 3 V
VIN_OP_H Minimum voltage hysteresis 1 V
IQ Non-switching input current; measured at VIN pin (3) VFB = +5%, VBIAS = 5 V 0.5 10 µA
ISD Shutdown quiescent current; measured at VIN pin VEN = 0 V, VIN = 12 V 0.57 7.5 µA
IB Current into BIAS pin (not switching) VFB = +5%, VBIAS = 5 V, Auto Mode Enabled  18.5 26 µA
ENABLE (EN PIN)
VEN Enable input-threshold voltage - rising VEN rising 1.0 1.263 1.365 V
VEN_HYST Enable threshold hysteresis 0.1 0.35 0.5 V
VEN_WAKE Enable Wake-up threshold 0.4 V
IEN Enable pin input current VIN = VEN = 12 V 1.5 50 nA
INTERNAL LDO (VCC PIN)
VCC Internal VCC voltage VBIAS = 0V 3.4 V
VBIAS = 3.3 V, 20 mA 3.2
VCC_UVLO VIN voltage at which Internal VCC under voltage lock-out is released IVCC = 0A 3.75 V
VCC_UVLO_HYST Internal VCC under voltage lock-out hysteresis Hysteresis below VCC_UVLO 1.2 V
VOLTAGE REFERENCE (FB PIN)
VFB Initial reference voltage accuracy for adjustable (1 V FB) versions VIN = 3.0 V to 36 V, FPWM Mode 0.985 1 1.015 V
IFB Input current from FB to AGND Adjustable versions only, VFB = 1 V 50 nA
CURRENT LIMITS
ISC_8 Short circuit high-side current Limit 8 A Variant, Duty cycle approaches 0% 11.5 13.8 15.7 A
ILS-LIMIT_8 Low-side current limit 8 9.2 10.5 A
IPEAK-MIN_8 Minimum Peak Inductor Current 1.9 A
IL-NEG_8 Negative current limit –6.4 –5.3 –3.9 A
IL-ZC Zero-cross current limit. Positive current direction is out of SW pin. Auto Mode, static measurement 70 mA
VHICCUP Hiccup threshold on FB pin 0.36 0.4 0.44 V
POWER GOOD (/RESET PIN)
V RESET-OV RESET upper threshold - Rising % of FB voltage 109.5 112 114.5 %
V RESET-UV RESET lower threshold - Falling % of FB voltage 93 95 97.5 %
V RESET_GUARD RESET UV threshold as percentage of steady state output voltage with output voltage and UV threshold, falling, read at the same TJ, and VIN. Falling 97 %
V RESET-HYS-FALLING RESET fallling threshold hysteresis % of FB voltage 1.3 %
V RESET-HYS-RISING RESET rising threshold hysteresis % of FB voltage 1.3 %
V RESET_VALID Minimum input voltage for proper RESET function Measured when VRESET < 0.4 V with 10 kOhm pullup to external 5 V 1.2 V
VOL RESET Low-level function output voltage 46.0 µA pull up to RESET pin, VIN = 1.0 V, VEN = 0 V 0.4 V
1 mA pull up to RESET pin, VIN = 12 V, VEN = 0 V 0.4
2 mA pull up to RESET pin, VIN = 12 V, VEN = 3.3 V 0.4
RRESET RESET ON resistance, VEN = 5 V, 1mA pull up current 44 125 Ω
RRESET RESET ON resistance, VEN = 0 V, 1mA pull up current 18 40 Ω
tRESET_FILTER RESET edge deglitch delay 10 26 45 µs
tRESET_ACT RESET active time Time FB must be valid before RESET is released. 1.2 2.1 3.75 ms
OSCILLATOR (RT and SYNC PINS)
fOSC Internal oscillator frequency RT = GND 1.90 2.2 2.42 MHz
fOSC Internal oscillator frequency RT = VCC 320 400 450 kHz
fFIXED_2.2MHz Oscillator frequency measured using maximum value of RT resistor to select 2.2 MHz RT = 6.81 kΩ 1.95 2.2 2.42 MHz
fFIXED_0.4MHz Oscillator frequency measured using minimum value of RT resistor to select 0.4 MHz RT = 40.2 kΩ 352 400 448 kHz
fADJ Center Trim oscillator frequency RT = 22.6 kΩ 630 700 770 kHz
VSYNCDL SYNC/MODE input voltage low 0.4 V
VSYNCDH SYNC/MODE input voltage high 1.7 V
VSYNCD_HYST SYNC/MODE input voltage hysteresis 0.185 1 V
RSYNC Internal pulldown resistor to ensure SYNC/MODE doesn't float 100 kΩ
tSYNC_EDGE High and Loww duration needed for synchronizing clock to be recognized on SYNC/MODE pin 100 ns
tMSYNC Time at one level needed to indicate FPWM or Auto Mode 7 20 µs
tLOCK Time needed for clock to lock to a valid synchronization signal RT = 39.2 kΩ 4.3 ms
SPREAD SPECTRUM
ΔFc+ Frequency increase of internal oscillator from spread spectrum 1 4 7.5 %
ΔFc- Frequency decrease of internal oscillator from spread spectrum -8 -4 -1 %
HIGH SIDE DRIVE (CBOOT PIN)
VCBOOT_UVLO Voltage on CBOOT pin compared to SW which will turnoff high-side switch 1.9 V
MOSFETS
RDS-ON-HS High-side MOSFET on-resistance Load = 1 A, CBOOT-SW = 3.2 V 21 39 mΩ
RDS-ON-LS Low-side MOSFET on-resistance Load = 1 A, CBOOT-SW = 3.2 V 13 25 mΩ
PWM LIMITS (SW PIN)
tON-MIN Minimum HS switch on-time VIN =18 V, VSYNC/MODE = 5 V, IOUT = 2A, RBOOT = 0 Ω 62 81 ns
tOFF-MIN Minimum HS switch off-time VIN = 5 V 70 103 ns
tON-MAX Maximum switch on-time HS timeout in dropout 6.9 8.9 11 µs
DMAX Maximum switch duty cycle While in frequency fold-back 98 %
fsw =1.85 MHz 87
START UP
tEN Turn-on delay VIN = 12 V, CVCC = 1 µF, time from EN high to first SW pulse if output starts at 0 V 0.82 1.2 ms
tSS Time from first SW pulse to VREF at 90%, of set point. 1.6 2.2 2.7 ms
tW Short circuit wait time ("hiccup" time) 40 ms