SNVSCU1A July   2025  – November 2025 TPSM65630

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 Output Voltage Selection
      2. 7.3.2 EN Pin and Use as VIN UVLO
      3. 7.3.3 Mode Selection
        1. 7.3.3.1 MODE/SYNC Pin Uses for Synchronization
        2. 7.3.3.2 Clock Locking
      4. 7.3.4 Adjustable Switching Frequency
      5. 7.3.5 Dual Random Spread Spectrum (DRSS)
      6. 7.3.6 Internal LDO, VCC UVLO, and BIAS Input
      7. 7.3.7 Bootstrap Voltage (BST Pin)
      8. 7.3.8 Soft Start and Recovery From Dropout
      9. 7.3.9 Safety Features
        1. 7.3.9.1 Power-Good Monitor
        2. 7.3.9.2 Overcurrent and Short-Circuit Protection
        3. 7.3.9.3 Hiccup
        4. 7.3.9.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Peak Current Mode Operation
        2. 7.4.2.2 Auto Mode Operation
          1. 7.4.2.2.1 Diode Emulation
        3. 7.4.2.3 FPWM Mode Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Choosing the Switching Frequency
        3. 8.2.2.3 FB for Adjustable or Fixed Output Voltage Mode
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 CBOOT
        7. 8.2.2.7 External UVLO
        8. 8.2.2.8 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TPSM656x0 is an easy-to-use, high-power density, synchronous buck DC-DC power module that operates from a 3V to 65V (70V tolerant) supply voltage. The TPSM656x0 has pin selectable fixed output voltages of 3.3V, 5V, or adjustable output configuration. With an integrated power controller, inductor, MOSFETs, and other necessary components, the TPSM656x0 delivers up to 3A, 2A, 1A DC load current with high efficiency and low input quiescent current in a very small design size. Although designed for simple implementation, this device offers flexibility to optimize the usage according to the target application.

The current-mode control architecture, with 30ns minimum on-time, allows high conversion ratios at high frequencies, fast transient response, and excellent load and line regulation. If the minimum on-time or minimum off-time does not support the desired conversion ratio, the switching frequency is automatically reduced. This feature allows regulation to be maintained during wide VIN variations.

This device is designed to minimize end-product cost and size while operating in high-performance industrial environments. The TPSM656x0 can be set to operate at fixed 400kHz, fixed 2.2MHz, or in adjustable mode from 300kHz to 2.2MHz by using the RT pin. An integrated compensation network combined with an accurate current limit scheme minimizes bill of material cost and component count.

The TPSM656x0 has been designed for low EMI. The device includes the following:

  • Mode pin-configurable ±5% or ±10% dual random spread spectrum (DRSS) frequency hopping
  • Symmetrical pin out minimizing parasitic package inductance
  • Operation over a frequency range above and below AM radio band
  • Pin-configurable for AUTO or FPWM mode along with external clock synchronization capabilities

These features can eliminate shielding and other expensive EMI mitigation measures.

The TPSM656x0 also includes protection features for robust system requirements:

  • An open-drain PGOOD indicator for power-rail sequencing and fault reporting
  • Precision enable input with hysteresis, providing:
    • Programmable line undervoltage lockout (UVLO)
    • Remote ON and OFF capability
  • Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits
  • Thermal shutdown with automatic recovery.

To use the device in reliability-conscious environments, the TPSM656x0 has a package with enlarged corner terminals for improved board level reliability.