SLVSGJ4C october   2022  – july 2023 TPSM82912 , TPSM82913 , TPSM82913E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Smart Config (S-CONF)
      2. 7.3.2  Device Enable (EN/SYNC)
      3. 7.3.3  Device Synchronization (EN/SYNC)
      4. 7.3.4  Spread Spectrum Modulation
      5. 7.3.5  Output Discharge
      6. 7.3.6  Undervoltage Lockout (UVLO)
      7. 7.3.7  Power-Good Output
      8. 7.3.8  Noise Reduction and Soft-Start Capacitor (NR/SS)
      9. 7.3.9  Current Limit and Short-Circuit Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed Frequency Pulse Width Modulation
      2. 7.4.2 Low Duty Cycle Operation
      3. 7.4.3 High Duty Cycle Operation (100% Duty Cycle)
      4. 7.4.4 Second Stage L-C Filter Compensation (Optional)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 External Component Selection
          1. 8.2.2.2.1 Switching Frequency Selection
          2. 8.2.2.2.2 Output Capacitor Selection
          3. 8.2.2.2.3 Ferrite Bead Selection for Second L-C Filter
          4. 8.2.2.2.4 Input Capacitor Selection
          5. 8.2.2.2.5 Setting the Output Voltage
          6. 8.2.2.2.6 NR/SS Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20220118-SS0I-PZTB-R9MK-ZWKTRTNZB0BQ-low.gifFigure 5-1 28-Pin QFN RDU Package (Top View)
Table 5-1 Pin Functions
PINI/ODESCRIPTION
NO.NAME

18

VINIPower supply input voltage pin
1, 2, 3, 5, 6, 7, 8, 9, 16, 17, 25, 26, 28PGNDPower ground connection

10, 11, 12, 13, 14, 15, 27

VOUT

O

Output connection. Connect recommended output capacitance from VOUT to PGND.

4

SW

NC

Switch pin of the power stage. Do not connect, leave floating.

19

PGOOpen-drain power-good output. This pin is pulled to GND when VOUT is below the power-good threshold. It requires a pull-up resistor to output a logic high. It can be left open or tied to GND if not used.

20

PSNSIPower sense ground. Connect directly to the ground plane.

21

NR/SSOA capacitor connected to this pin sets the soft-start time and low frequency noise level of the device.

22

FBIFeedback pin of the device

23

S-CONFOSmart Configuration pin. This pin configures the operation modes of the device. See Table 7-1.

24

EN/SYNC

I

Enable/Disable pin including threshold-comparator. Connect to logic low to disable the device. Pull high to enable the device. This pin has an internal pull-down resistor of typically 500 kΩ when the device is disabled. Apply a clock to this pin to synchronize the device.