SLUSEU3 January   2024 TPSM843820E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Module)
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VIN Pins and VIN UVLO
      2. 6.3.2  Enable and Adjustable UVLO
      3. 6.3.3  Adjusting the Output Voltage
      4. 6.3.4  Switching Frequency Selection
      5. 6.3.5  Switching Frequency Synchronization to an External Clock
        1. 6.3.5.1 Internal PWM Oscillator Frequency
        2. 6.3.5.2 Loss of Synchronization
        3. 6.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 6.3.6  Ramp Amplitude Selection
      7. 6.3.7  Soft Start and Prebiased Output Start-Up
      8. 6.3.8  Mode Pin
      9. 6.3.9  Power Good (PGOOD)
      10. 6.3.10 Current Protection
        1. 6.3.10.1 Positive Inductor Current Protection
        2. 6.3.10.2 Negative Inductor Current Protection
      11. 6.3.11 Output Overvoltage and Undervoltage Protection
      12. 6.3.12 Overtemperature Protection
      13. 6.3.13 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Discontinuous Conduction Mode During Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 1.0V Output, 1.5MHz Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Switching Frequency
          2. 7.2.1.2.2  Output Inductor Selection
          3. 7.2.1.2.3  Output Capacitor
          4. 7.2.1.2.4  Input Capacitor
          5. 7.2.1.2.5  Adjustable Undervoltage Lockout
          6. 7.2.1.2.6  Output Voltage Resistors Selection
          7. 7.2.1.2.7  Bootstrap Capacitor Selection
          8. 7.2.1.2.8  BP5 Capacitor Selection
          9. 7.2.1.2.9  PGOOD Pullup Resistor
          10. 7.2.1.2.10 Current Limit Selection
          11. 7.2.1.2.11 Soft-Start Time Selection
          12. 7.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 7.2.1.2.13 MODE Pin
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Performance
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-20231024-SS0I-V2FC-XZZZ-ZC5NTTQDT23C-low.svg Figure 4-1 SIT Package15-Pin uSiP(Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
FB 1 I Feedback pin for output voltage regulation. Connect this pin to the midpoint of a resistor divider to set the output voltage.
AGND 2 — Ground return for internal analog circuits
BP5 3 O Internal 5V regulator output. Bypass this pin with a 2.2μF capacitor to AGND.
PG 4 O Open-drain power-good indicator
MODE 5 I A resistor to ground selects the current limit, soft-start rate, and PWM ramp amplitude.
EN 6 I Enable pin. Float to enable, enable and disable with an external signal, or adjust the input undervoltage lockout with a resistor divider.
PGND 7, 8, 9 — Ground return for the power stage. This pin is internally connected to the source of the low-side MOSFET.
VIN 10 I Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A 47nF to 100nF capacitor from VIN to PGND close to IC is required.
SW 11 DNC Switch node of the module, used for monitoring only
BOOT 12 DNC Supply for the internal high-side MOSFET gate driver. This pin is monitoring only because the capacitor to SW pin is integrated
SYNC/FSEL 13 I Frequency select and external clock synchronization. A resistor to ground sets the switching frequency of the device. An external clock can also be applied to this pin to synchronize the switching frequency.
VOUT 14 O Buck output voltage. Connect output capacitors to this node.
PAD/PGND 15 — Thermal pad connected to PGND
(1) I = input, O = output