SLVSI55A December   2025  – December 2025 TPSM8F7420 , TPSM8F7620

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Bias Supply Regulator (VCC)
      3. 7.3.3  Device Configuration Pin (MSEL)
      4. 7.3.4  Multiphase Output Configuration
      5. 7.3.5  Enable and Adjustable UVLO
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Device Synchronization (SYNC)
        1. 7.3.7.1 Clock Locking
      8. 7.3.8  Adjustable Output Voltage (FB)
      9. 7.3.9  Control Loop Compensation (COMP)
      10. 7.3.10 Slope Compensation
      11. 7.3.11 Power-Good Output Voltage Monitoring
      12. 7.3.12 Output Discharge
      13. 7.3.13 Soft-Start (SS)
      14. 7.3.14 Overcurrent Protection (OCP)
      15. 7.3.15 Temperature Output
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 Peak Current Mode Operation
        2. 7.4.3.2 Diode Emulation
        3. 7.4.3.3 FPWM Mode Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 7.4.3.5 Dropout
        6. 7.4.3.6 Recovery from Dropout
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Module Operating Area
        3. 8.2.2.3  Choosing the Switching Frequency
        4. 8.2.2.4  Setting the Output Voltage
        5. 8.2.2.5  Integrated Inductor Considerations
        6. 8.2.2.6  Input Capacitor Selection
        7. 8.2.2.7  Soft-Start Capacitor
        8. 8.2.2.8  VCC and BOOT Capacitors
        9. 8.2.2.9  Output Capacitor Selection
        10. 8.2.2.10 Compensation Selection
      3. 8.2.3 Application Curves
    3. 8.3 2-PH Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves 2-PH
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Thermal Design and Layout
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • APG|112
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Device Synchronization (SYNC)

The SYNC pin is used to synchronize the internal oscillator to an external clock. When synchronized to an external clock, the TPSM8F7x20 operates in FPWM. The internal oscillator can be synchronized to a positive edge into the SYNC pin. The rising edge voltage at the SYNC pin must exceed the SYNC amplitude threshold of VIH(sync) to trip the internal synchronization pulse detector. The minimum SYNC rising pulse and falling pulse durations must be longer than tSYNC(IH) and tSYNC(IL) respectively. The TPSM8F7x20 switching action can be synchronized to an external clock from 320kHz to 2.6MHz. When synchronizing to an external clock, the frequency input must be within approximately ±20% of the internal clock frequency programmed by the RT pin. This action prevents large frequency changes in the event of loss of synchronization. This action is also used to set the slope compensation for secondary devices.

TPSM8F7420 TPSM8F7620 Typical SYNC Waveform
This image shows the conditions needed for detection of a synchronization signal.
Figure 7-4 Typical SYNC Waveform