SLOS757F December   2011  – May 2017 TRF7962A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Functional Block Diagram
    2. 6.2  Power Supplies
    3. 6.3  Supply Arrangements
    4. 6.4  Supply Regulator Settings
    5. 6.5  Power Modes
    6. 6.6  Receiver - Analog Section
      1. 6.6.1 Main and Auxiliary Receiver
      2. 6.6.2 Receiver Gain and Filter Stages
    7. 6.7  Receiver - Digital Section
      1. 6.7.1 Received Signal Strength Indicator (RSSI)
        1. 6.7.1.1 Internal RSSI - Main and Auxiliary Receivers
        2. 6.7.1.2 External RSSI
    8. 6.8  Oscillator Section
    9. 6.9  Transmitter - Analog Section
    10. 6.10 Transmitter - Digital Section
    11. 6.11 Transmitter - External Power Amplifier or Subcarrier Detector
    12. 6.12 Communication Interface
      1. 6.12.1 General Introduction
      2. 6.12.2 FIFO Operation
      3. 6.12.3 Parallel Interface Mode
      4. 6.12.4 Reception of Air Interface Data
      5. 6.12.5 Data Transmission to MCU
      6. 6.12.6 Serial Interface Communication (SPI)
        1. 6.12.6.1 Serial Interface Mode Without Slave Select (SS)
        2. 6.12.6.2 Serial Interface Mode With Slave Select (SS)
      7. 6.12.7 Direct Mode
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1  Command Codes
      2. 6.13.2  Reset FIFO (0x0F)
      3. 6.13.3  Transmission With CRC (0x11)
      4. 6.13.4  Transmission Without CRC (0x10)
      5. 6.13.5  Transmit Next Time Slot (0x14)
      6. 6.13.6  Block Receiver (0x16)
      7. 6.13.7  Enable Receiver (0x17)
      8. 6.13.8  Test Internal RF (RSSI at RX Input With TX On) (0x18)
      9. 6.13.9  Test External RF (RSSI at RX Input With TX Off) (0x19)
      10. 6.13.10 Register Preset
    14. 6.14 Register Description
      1. 6.14.1 Register Overview
        1. 6.14.1.1 Main Configuration Registers
          1. 6.14.1.1.1 Chip Status Control Register (0x00)
          2. 6.14.1.1.2 ISO Control Register (0x01)
        2. 6.14.1.2 Protocol Subsetting Registers
          1. 6.14.1.2.1 TX Pulse Length Control Register (0x06)
          2. 6.14.1.2.2 RX No Response Wait Time Register (0x07)
          3. 6.14.1.2.3 RX Wait Time Register (0x08)
          4. 6.14.1.2.4 Modulator and SYS_CLK Control Register (0x09)
          5. 6.14.1.2.5 RX Special Setting Register (0x0A)
          6. 6.14.1.2.6 Regulator and I/O Control Register (0x0B)
        3. 6.14.1.3 Status Registers
          1. 6.14.1.3.1 IRQ Status Register (0x0C)
          2. 6.14.1.3.2 Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
          3. 6.14.1.3.3 RSSI Levels and Oscillator Status Register (0x0F)
        4. 6.14.1.4 Test Registers
          1. 6.14.1.4.1 Test Register (0x1A)
          2. 6.14.1.4.2 Test Register (0x1B)
        5. 6.14.1.5 FIFO Control Registers
          1. 6.14.1.5.1 FIFO Status Register (0x1C)
          2. 6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7962A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 System Design
      1. 7.2.1 Layout Considerations
      2. 7.2.2 Impedance Matching TX_Out (Pin 5) to 50 Ω
      3. 7.2.3 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Community Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Overview

Features

  • Completely Integrated Protocol Handling for ISO/IEC 15693 and ISO/IEC 18000-3
  • Input Voltage Range: 2.7 VDC to 5.5 VDC
  • Programmable Output Power:
    +20 dBm (100 mW) or +23 dBm (200 mW)
  • Programmable I/O Voltage Levels:
    1.8 VDC to 5.5 VDC
  • Programmable System Clock Frequency Output (RF, RF/2, RF/4)
  • Programmable Modulation Depth
  • Dual Receiver Architecture With RSSI for Elimination of "Read Holes" and Adjacent Reader System or Ambient In-Band Noise Detection
  • Programmable Power Modes for Ultra-Low-Power System Design (Power Down <0.5 µA)
  • Parallel or SPI Interface
  • Integrated Voltage Regulator for Microcontroller Supply
  • Temperature Range: –25°C to 85°C
  • 32-Pin QFN Package (5 mm × 5 mm) (RHB)

Applications

  • Product Authentication
  • Access Control
  • Digital Door Locks
  • Library Management
  • Medical Systems
  • Remote Sensor Applications

Description

The TRF7962A device is an integrated analog front-end (AFE) and data-framing device for a 13.56-MHz RFID reader/writer system that supports ISO/IEC 15693. Built-in programming options make it suitable for a wide range of applications for proximity and vicinity identification systems.

The reader is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed.

The TRF7962A device supports data rates 6 kbps and 26 kbps with all framing and synchronization tasks for the ISO protocols onboard. The device also supports reader/writer mode for NFC Forum tag type 5. NFC Forum tag type 5 is supported with the built-in protocol decoders used in Direct Mode 2. NFC Forum tag type 1 requires the use of Direct Mode 0. Other standards and custom protocols can also be implemented by using Direct Mode 0. Direct Mode 0 lets the user fully control the AFE and also gain access to the raw subcarrier data or the unframed, but already ISO-formatted, data and the associated (extracted) clock signal.

The receiver system has a dual-input receiver architecture to maximize communication robustness. The receivers also include various automatic and manual gain control options. The received signal strength from transponders, ambient sources, or internal levels is available in the RSSI register.

A SPI or parallel interface can be used for the communication between the MCU and the TRF7962A reader. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 12-byte FIFO register. For direct transmit or receive functions, the encoders or decoders can be bypassed so the MCU can process the data in real time.

The TRF7962A device supports a wide supply voltage range of 2.7 V to 5.5 V and data communication levels from 1.8 V to 5.5 V for the MCU I/O interface.

The transmitter has selectable output power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply and supports OOK and ASK modulation with selectable modulation depth.

The built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and additional external circuits within the reader system.

Start evaluating the TRF7962A transceiver IC with the TRF7960AEVM or the TRF7960ATB of the superset device.

Documentation, Tools, Reference Designs, and Software, Samples

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
TRF7962ARHB VQFN (32) 5 mm × 5 mm
For more information, see Section 9, Mechanical Packaging and Orderable Information.

Application Block Diagram

Figure 1-1 shows a typical application block diagram.

TRF7962A app_bd_slos732.gif Figure 1-1 Application Block Diagram