SLOS757G December   2011  – March 2020 TRF7962A


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Functional Block Diagram
    2. 6.2  Power Supplies
    3. 6.3  Supply Arrangements
    4. 6.4  Supply Regulator Settings
    5. 6.5  Power Modes
    6. 6.6  Receiver – Analog Section
      1. 6.6.1 Main and Auxiliary Receiver
      2. 6.6.2 Receiver Gain and Filter Stages
    7. 6.7  Receiver – Digital Section
      1. 6.7.1 Received Signal Strength Indicator (RSSI)
        1. Internal RSSI – Main and Auxiliary Receivers
        2. External RSSI
    8. 6.8  Oscillator Section
    9. 6.9  Transmitter - Analog Section
    10. 6.10 Transmitter - Digital Section
    11. 6.11 Transmitter – External Power Amplifier or Subcarrier Detector
    12. 6.12 Communication Interface
      1. 6.12.1 General Introduction
      2. 6.12.2 FIFO Operation
      3. 6.12.3 Parallel Interface Mode
      4. 6.12.4 Reception of Air Interface Data
      5. 6.12.5 Data Transmission to MCU
      6. 6.12.6 Serial Interface Communication (SPI)
        1. Serial Interface Mode Without Slave Select (SS)
        2. Serial Interface Mode With Slave Select (SS)
      7. 6.12.7 Direct Mode
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1  Command Codes
      2. 6.13.2  Reset FIFO (0x0F)
      3. 6.13.3  Transmission With CRC (0x11)
      4. 6.13.4  Transmission Without CRC (0x10)
      5. 6.13.5  Transmit Next Time Slot (0x14)
      6. 6.13.6  Block Receiver (0x16)
      7. 6.13.7  Enable Receiver (0x17)
      8. 6.13.8  Test Internal RF (RSSI at RX Input With TX On) (0x18)
      9. 6.13.9  Test External RF (RSSI at RX Input With TX Off) (0x19)
      10. 6.13.10 Register Preset
    14. 6.14 Register Description
      1. 6.14.1 Register Overview
        1. Main Configuration Registers
          1. Chip Status Control Register (0x00)
          2. ISO Control Register (0x01)
        2. Protocol Subsetting Registers
          1. TX Pulse Length Control Register (0x06)
          2. RX No Response Wait Time Register (0x07)
          3. RX Wait Time Register (0x08)
          4. Modulator and SYS_CLK Control Register (0x09)
          5. RX Special Setting Register (0x0A)
          6. Regulator and I/O Control Register (0x0B)
        3. Status Registers
          1. IRQ Status Register (0x0C)
          2. Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
          3. RSSI Levels and Oscillator Status Register (0x0F)
        4. Test Registers
          1. Test Register (0x1A)
          2. Test Register (0x1B)
        5. FIFO Control Registers
          1. FIFO Status Register (0x1C)
          2. TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7962A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 System Design
      1. 7.2.1 Layout Considerations
      2. 7.2.2 Impedance Matching TX_Out (Pin 5) to 50 Ω
      3. 7.2.3 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Serial Interface Mode With Slave Select (SS)

The serial interface is in reset while the Slave Select signal is high. Serial data in (MOSI) changes on the falling edge and is validated in the reader on the rising edge (see Figure 6-17). Communication is terminated when the Slave Select signal goes high.

All words must be 8 bits long with the MSB transmitted first.

TRF7962A spi_w_slave_select_slos732.gifFigure 6-17 SPI With Slave Select Timing

The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data changes on the falling edge, and is validated in the reader on the rising edge, as shown in Figure 6-17. During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is validated at the eighth rising edge of SCLK, after half a clock cycle, valid data can be read on the MISO pin at the falling edge of SCLK. It takes eight clock edges to read out the full byte (MSB first).

When using the hardware SPI (for example, an MSP430 hardware SPI) to implement this feature, care must be taken to switch the SCLK polarity after write phase for proper read operation. The example clock polarity for the Figure 6-17 shows the MSP430-specific environment in the write-mode and read-mode boxes. See the USART-SPI chapter for any specific microcontroller family for further information on the setting the appropriate clock polarity. This clock polarity switch must be done for all read (single or continuous) operations. The MOSI (serial data out) should not have any transitions (all high or all low) during the read cycle. The Slave Select should be low during the whole write and read operation.

See Section 5.6, Switching Characteristics, for the timing values shown in Figure 6-17.

Figure 6-18 shows the continuous read operation.

TRF7962A cont_read_operation_spi_ss_slos732.gifFigure 6-18 Continuous Read Operation Using SPI With Slave Select
TRF7962A cont_read_registers_spi_ss_slos732.pngFigure 6-19 Continuous Read of Registers 0x00 to 0x05 Using SPI With SS

Figure 6-20 shows performing a Single Slot Inventory Command as an example. Reader registers (in this example) are configured for 5-VDC input and default operation. Full sequences for other settings and protocols can be downloaded from

TRF7962A inventory_command_slos732.pngFigure 6-20 Inventory Command Sent From MCU to TRF7962A

The TRF7962A reads these bytes from the MCU and then sends out Request Flags, Inventory Command, and Mask over the air to the ISO/IEC 15693 transponder. After these three bytes have been transmitted, an interrupt occurs from the reader to indicate back to the MCU that the transmission has been completed. In the example shown in Figure 6-21, this IRQ occurs approximately 1.6 ms after the SS line goes high after the Inventory command is sent out.

TRF7962A irq_after_inventory_command_slos732.pngFigure 6-21 IRQ After Inventory Command

The IRQ Status register read (0x6C) yields 0x80, which indicates that TX is complete. This is followed by dummy clock and reset of FIFO with dummy clock. Then, if a tag is in the field and no error is detected by the reader, a second interrupt is expected and occurs (in this example) approximately 4 ms after first IRQ is read and cleared.

In the continuation of the example (see Figure 6-22), the IRQ Status register is read using method previously recommended, followed by a single read of the FIFO Status register, which indicates that there are at least 9 bytes to be read out.

TRF7962A irq_status_reg_fifo_status_reg_read_slos732.pngFigure 6-22 IRQ Status Register Read Followed by FIFO Status Register Read

This is followed by a continuous read of the FIFO (see Figure 6-23). The first byte is 0x00 for no error. The next byte is the DSFID (usually shipped by manufacturer as 0x00), then the UID, shown here up to the next most significant byte (MSByte), the MFG code (0x07 to indicate TI silicon).

TRF7962A cont_read_fifo_slos732.pngFigure 6-23 Continuous Read of FIFO

This is followed by another IRQ approximately 160 µs later, as there is still one byte in FIFO, the MSB of the UID, which must be retrieved (see Figure 6-24). IRQ register read shows RX is complete and FIFO register status shows one byte available, as expected and it is the E0, indicating ISO/IEC 15693 transponder.

TRF7962A irq_with_one_byte_fifo_slos732.pngFigure 6-24 IRQ With One Byte in FIFO

TI recommends resetting the FIFO after receiving data. Additionally, the RSSI value of the tag can be read out at this time. In the example in Figure 6-25, the transponder is very close to the antenna, so a value of 0x7E is recovered.

TRF7962A reset_fifo_read_rssi_slos732.pngFigure 6-25 Reset FIFO and Read RSSI