SLOS757G December   2011  – March 2020 TRF7962A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Functional Block Diagram
    2. 6.2  Power Supplies
    3. 6.3  Supply Arrangements
    4. 6.4  Supply Regulator Settings
    5. 6.5  Power Modes
    6. 6.6  Receiver – Analog Section
      1. 6.6.1 Main and Auxiliary Receiver
      2. 6.6.2 Receiver Gain and Filter Stages
    7. 6.7  Receiver – Digital Section
      1. 6.7.1 Received Signal Strength Indicator (RSSI)
        1. 6.7.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.7.1.2 External RSSI
    8. 6.8  Oscillator Section
    9. 6.9  Transmitter - Analog Section
    10. 6.10 Transmitter - Digital Section
    11. 6.11 Transmitter – External Power Amplifier or Subcarrier Detector
    12. 6.12 Communication Interface
      1. 6.12.1 General Introduction
      2. 6.12.2 FIFO Operation
      3. 6.12.3 Parallel Interface Mode
      4. 6.12.4 Reception of Air Interface Data
      5. 6.12.5 Data Transmission to MCU
      6. 6.12.6 Serial Interface Communication (SPI)
        1. 6.12.6.1 Serial Interface Mode Without Slave Select (SS)
        2. 6.12.6.2 Serial Interface Mode With Slave Select (SS)
      7. 6.12.7 Direct Mode
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1  Command Codes
      2. 6.13.2  Reset FIFO (0x0F)
      3. 6.13.3  Transmission With CRC (0x11)
      4. 6.13.4  Transmission Without CRC (0x10)
      5. 6.13.5  Transmit Next Time Slot (0x14)
      6. 6.13.6  Block Receiver (0x16)
      7. 6.13.7  Enable Receiver (0x17)
      8. 6.13.8  Test Internal RF (RSSI at RX Input With TX On) (0x18)
      9. 6.13.9  Test External RF (RSSI at RX Input With TX Off) (0x19)
      10. 6.13.10 Register Preset
    14. 6.14 Register Description
      1. 6.14.1 Register Overview
        1. 6.14.1.1 Main Configuration Registers
          1. 6.14.1.1.1 Chip Status Control Register (0x00)
          2. 6.14.1.1.2 ISO Control Register (0x01)
        2. 6.14.1.2 Protocol Subsetting Registers
          1. 6.14.1.2.1 TX Pulse Length Control Register (0x06)
          2. 6.14.1.2.2 RX No Response Wait Time Register (0x07)
          3. 6.14.1.2.3 RX Wait Time Register (0x08)
          4. 6.14.1.2.4 Modulator and SYS_CLK Control Register (0x09)
          5. 6.14.1.2.5 RX Special Setting Register (0x0A)
          6. 6.14.1.2.6 Regulator and I/O Control Register (0x0B)
        3. 6.14.1.3 Status Registers
          1. 6.14.1.3.1 IRQ Status Register (0x0C)
          2. 6.14.1.3.2 Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
          3. 6.14.1.3.3 RSSI Levels and Oscillator Status Register (0x0F)
        4. 6.14.1.4 Test Registers
          1. 6.14.1.4.1 Test Register (0x1A)
          2. 6.14.1.4.2 Test Register (0x1B)
        5. 6.14.1.5 FIFO Control Registers
          1. 6.14.1.5.1 FIFO Status Register (0x1C)
          2. 6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7962A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 System Design
      1. 7.2.1 Layout Considerations
      2. 7.2.2 Impedance Matching TX_Out (Pin 5) to 50 Ω
      3. 7.2.3 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.14.1.2.6 Regulator and I/O Control Register (0x0B)

Table 6-24 describes the bit fields of the Regulator and I/O Control register. This register controls the three voltage regulators.

Default Value: 0x87, set at POR = H or EN = L

Table 6-24 Regulator and I/O Control Register (0x0B)

BIT NO. BIT NAME FUNCTION DESCRIPTION
B7 auto_reg 0 = Manual system
1 = Automatic system

Automatic system settings:

VDD_RF = VIN – 250 mV

VDD_A = VIN – 250 mV

VDD_X = VIN – 250 mV, but not higher than 3.4 V

Manual system settings:

See B2 to B0
B6 en_ext_pa Support for external power amplifier Internal peak detectors are disabled, receiver inputs (RX_IN1 and RX_IN2) accept externally demodulated subcarrier. At the same time, the ASK/OOK pin becomes modulation output for external TX amplifier.
B5 io_low 1 = Enable low peripheral communication voltage When B5 = 1, maintains the output driving capabilities of the I/O pins connected to the level shifter under low-voltage operation. Should be set 1 when VDD_I/O voltage is 1.8 V to 2.7 V.
B4 Unused No function Default is 0.
B3 Unused No function Default is 0.
B2 vrs2 Voltage set. B2 is the MSB. vrs3_5 = L:

VDD_RF, VDD_A, VDD_X range is 2.7 V to 3.4 V.

See Table 6-25, Table 6-26, Table 6-27, and Table 6-28.
B1 vrs1
B0 vrs0

Table 6-25 Supply Regulator Setting, Manual 5-V System

REGISTER OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2 B1 B0
00 1 5-V system
0B 0 Manual regulator setting
0B 0 1 1 1 VDD_RF = 5 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0B 0 1 1 0 VDD_RF = 4.9 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0B 0 1 0 1 VDD_RF = 4.8 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0B 0 1 0 0 VDD_RF = 4.7 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0B 0 0 1 1 VDD_RF = 4.6 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0B 0 0 1 0 VDD_RF = 4.5 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0B 0 0 0 1 VDD_RF = 4.4 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0B 0 0 0 0 VDD_RF = 4.3 V, VDD_A = 3.5 V, VDD_X = 3.4 V

Table 6-26 Supply Regulator Setting, Manual 3-V System

REGISTER OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2 B1 B0
00 0 3-V system
0B 0 Manual regulator setting
0B 0 1 1 1 VDD_RF = 3.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 1 1 0 VDD_RF = 3.3 V, VDD_A = 3.3 V, VDD_X = 3.3 V
0B 0 1 0 1 VDD_RF = 3.2 V, VDD_A = 3.2 V, VDD_X = 3.2 V
0B 0 1 0 0 VDD_RF = 3.1 V, VDD_A = 3.1 V, VDD_X = 3.1 V
0B 0 0 1 1 VDD_RF = 3.0 V, VDD_A = 3.0 V, VDD_X = 3.0 V
0B 0 0 1 0 VDD_RF = 2.9 V, VDD_A = 2.9 V, VDD_X = 2.9 V
0B 0 0 0 1 VDD_RF = 2.8 V, VDD_A = 2.8 V, VDD_X = 2.8 V
0B 0 0 0 0 VDD_RF = 2.7 V, VDD_A = 2.7 V, VDD_X = 2.7 V

Table 6-27 Supply Regulator Setting, Automatic 5-V System

REGISTER OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2 (1) B1 B0
00 1 5-V system
0B 1 x 1 1 Automatic regulator setting with 250-mV difference
0B 1 x 1 0 Automatic regulator setting with 350-mV difference
0B 1 x 0 0 Automatic regulator setting with 400-mV difference
(1) x = don't care

Table 6-28 Supply Regulator Setting, Automatic 3-V System

REGISTER OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2 (1) B1 B0
00 0 3-V system
0B 1 x 1 1 Automatic regulator setting with 250-mV difference
0B 1 x 1 0 Automatic regulator setting with 350-mV difference
0B 1 x 0 0 Automatic regulator setting with 400-mV difference