SLLSE09I November   2009  – December 2019 TUSB1210

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Analog I/O Electrical Characteristics
    6. 6.6  Digital I/O Electrical Characteristics
    7. 6.7  Digital IO Pins (Non-ULPI)
    8. 6.8  PHY Electrical Characteristics
    9. 6.9  Pullup/Pulldown Resistors
    10. 6.10 OTG Electrical Characteristics
    11. 6.11 OTG ID Electrical
    12. 6.12 Power Characteristics
    13. 6.13 Switching Characteristics
    14. 6.14 Timing Requirements
      1. 6.14.1 Timing Parameter Definitions
      2. 6.14.2 Interface Target Frequencies
    15. 6.15 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Processor Subsystem
        1. 7.3.1.1 Clock Specifications
          1. 7.3.1.1.1 USB PLL Reference Clock
          2. 7.3.1.1.2 ULPI Input Clock Configuration
          3. 7.3.1.1.3 ULPI Output Clock Configuration
          4. 7.3.1.1.4 Clock 32 kHz
          5. 7.3.1.1.5 Reset
        2. 7.3.1.2 USB Transceiver
          1. 7.3.1.2.1 PHY Electrical Characteristics
            1. 7.3.1.2.1.1 LS/FS Single-Ended Receivers
            2. 7.3.1.2.1.2 LS/FS Differential Receiver
            3. 7.3.1.2.1.3 LS/FS Transmitter
            4. 7.3.1.2.1.4 HS Differential Receiver
            5. 7.3.1.2.1.5 HS Differential Transmitter
            6. 7.3.1.2.1.6 UART Transceiver
          2. 7.3.1.2.2 OTG Characteristics
    4. 7.4 Device Functional Modes
      1. 7.4.1 TUSB1210 Modes vs ULPI Pin Status
    5. 7.5 Register Map
      1. Table 7. USB Register Summary
      2. 7.5.1    VENDOR_ID_LO
      3. 7.5.2    VENDOR_ID_HI
      4. 7.5.3    PRODUCT_ID_LO
      5. 7.5.4    PRODUCT_ID_HI
      6. 7.5.5    FUNC_CTRL
      7. 7.5.6    FUNC_CTRL_SET
      8. 7.5.7    FUNC_CTRL_CLR
      9. 7.5.8    IFC_CTRL
      10. 7.5.9    IFC_CTRL_SET
      11. 7.5.10   IFC_CTRL_CLR
      12. 7.5.11   OTG_CTRL
      13. 7.5.12   OTG_CTRL_SET
      14. 7.5.13   OTG_CTRL_CLR
      15. 7.5.14   USB_INT_EN_RISE
      16. 7.5.15   USB_INT_EN_RISE_SET
      17. 7.5.16   USB_INT_EN_RISE_CLR
      18. 7.5.17   USB_INT_EN_FALL
      19. 7.5.18   USB_INT_EN_FALL_SET
      20. 7.5.19   USB_INT_EN_FALL_CLR
      21. 7.5.20   USB_INT_STS
      22. 7.5.21   USB_INT_LATCH
      23. 7.5.22   DEBUG
      24. 7.5.23   SCRATCH_REG
      25. 7.5.24   SCRATCH_REG_SET
      26. 7.5.25   SCRATCH_REG_CLR
      27. 7.5.26   VENDOR_SPECIFIC1
      28. 7.5.27   VENDOR_SPECIFIC1_SET
      29. 7.5.28   VENDOR_SPECIFIC1_CLR
      30. 7.5.29   VENDOR_SPECIFIC2
      31. 7.5.30   VENDOR_SPECIFIC2_SET
      32. 7.5.31   VENDOR_SPECIFIC2_CLR
      33. 7.5.32   VENDOR_SPECIFIC1_STS
      34. 7.5.33   VENDOR_SPECIFIC1_LATCH
      35. 7.5.34   VENDOR_SPECIFIC3
      36. 7.5.35   VENDOR_SPECIFIC3_SET
      37. 7.5.36   VENDOR_SPECIFIC3_CLR
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Host or OTG, ULPI Input Clock Mode Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Unused Pins Connection
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Device, ULPI Output Clock Mode Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Unused Pins Connection
        3. 8.2.2.3 Application Curve
    3. 8.3 External Components
  9. Power Supply Recommendations
    1. 9.1 TUSB1210 Power Supply
    2. 9.2 Ground
    3. 9.3 Power Providers
    4. 9.4 Power Modules
      1. 9.4.1 VDD33 Regulator
      2. 9.4.2 VDD18 Supply
      3. 9.4.3 VDD15 Regulator
    5. 9.5 Power Consumption
  10. 10Layout
    1. 10.1 TUSB121x USB2.0 Product Family Board Layout Recommendations
    2. 10.2 Layout Guidelines
    3. 10.3 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • USB2.0 PHY Transceiver Chip, Designed to Interface With a USB Controller Through a ULPI Interface, Fully Compliant With:
    • Universal Serial Bus Specification Rev. 2.0
    • On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3
    • UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
    • ULPI 12-pin SDR Interface
  • DP/DM Line External Component Compensation (Patent #US7965100 B1)
  • Interfaces to Host, Peripheral and OTG Device Cores; Optimized for Portable Devices or System ASICs With Built-in USB OTG Device Core
  • Complete USB OTG Physical Front-End That Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
  • VBUS Overvoltage Protection Circuitry Protects VBUS Pin in Range –2 V to 20 V
  • Internal 5-V Short-Circuit Protection of DP, DM, and ID Pins for Cable Shorting to VBUS Pin
  • ULPI Interface:
    • I/O Interface (1.8 V) Optimized for Nonterminated 50-Ω Line Impedance
    • ULPI CLOCK Pin (60 MHz) Supports Both Input and Output Clock Configurations
    • Fully Programmable ULPI-Compliant Register Set
  • Full Industrial Grade Operating Temperature Range From –40°C to 85°C
  • Available in a 32-Pin Quad Flat No Lead [QFN (RHB)] Package