SLLSEQ8D October   2015  – May 2017 TUSB320HAI , TUSB320LAI

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Cables, Adapters, and Direct Connect Devices
        1. 7.1.1.1 USB Type-C Receptacles and Plugs
        2. 7.1.1.2 USB Type-C Cables
        3. 7.1.1.3 Legacy Cables and Adapters
        4. 7.1.1.4 Direct Connect Devices
        5. 7.1.1.5 Audio Adapters
    2. 7.2 Feature Description
      1. 7.2.1 Port Role Configuration
        1. 7.2.1.1 Downstream Facing Port (DFP) - Source
        2. 7.2.1.2 Upstream Facing Port (UFP) - Sink
        3. 7.2.1.3 Dual Role Port (DRP)
      2. 7.2.2 Type-C Current Mode
      3. 7.2.3 Accessory Support
        1. 7.2.3.1 Audio Accessory
        2. 7.2.3.2 Debug Accessory
      4. 7.2.4 I2C and GPIO Control
      5. 7.2.5 VBUS Detection
    3. 7.3 Device Functional Modes
      1. 7.3.1 Unattached Mode
      2. 7.3.2 Active Mode
      3. 7.3.3 Dead Battery Mode
      4. 7.3.4 Shutdown Mode
    4. 7.4 Programming
    5. 7.5 Register Maps
      1. 7.5.1 CSR Registers (address = 0x00 - 0x07)
      2. 7.5.2 CSR Registers (address = 0x08)
      3. 7.5.3 CSR Registers (address = 0x09)
      4. 7.5.4 CSR Registers (address = 0x0A)
      5. 7.5.5 CSR Registers (address = 0x45)
      6. 7.5.6 CSR Registers (address = 0xA0)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 DRP in I2C Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DFP in I2C Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 UFP in I2C Mode
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Initialization Setup
      1. 8.3.1 TUSB320LA Initialization Procedure
      2. 8.3.2 TUSB320HA Initialization Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TUSB320 device is a Type-C configuration channel logic and port controller. The TUSB320 device can detect when a Type-C device is attached, what type of device is attached, the orientation of the cable, and power capabilities (both detection and broadcast). The TUSB320 device can be used in a source application (DFP), in a sink application (UFP), or a combination source/sink application (DRP).

8.2 Typical Application

8.2.1 DRP in I2C Mode

Figure 10 and Figure 11 show a Type-C configuration for the DRP mode.

TUSB320LAI TUSB320HAI app_typ_01_drp_sllsen9_320.gif Figure 10. TUSB320 in DRP Mode Supporting Default Implementation
TUSB320LAI TUSB320HAI app_typ_04_drp_sllsen9_320.gif Figure 11. TUSB320 in DRP Mode Supporting Advanced Power Delivery

Figure 12 shows the TUSB320 device configured as a DRP in I2C mode.

TUSB320LAI TUSB320HAI DRP_schematic_SLLSEQ8.gif Figure 12. DRP in I2C Mode Schematic

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 13:

Table 13. Design Requirements for DRP in I2C Mode

DESIGN PARAMETER VALUE
VDD (2.75 V to 5 V) VBAT (less than 5 V)
Mode (I2C or GPIO) I2C: ADDR pin must be pulled down or pulled up
I2C address (0x67 or 0x47) 0x47: ADDR pin must be pulled low or tied to GND
Type-C port type (UFP, DFP, or DRP) DRP: PORT pin is NC
Shutdown support No

8.2.1.2 Detailed Design Procedure

The TUSB320 device supports a VDD in the range of 2.75 V to 5 V. In this particular use case, VBAT which must be in the required VDD range is connected to the VDD pin. A 100-nF capacitor is placed near VDD.

The TUSB320 device is placed into I2C mode by either pulling the ADDR pin high or low. In this case, the ADDR pin is tied to GND which results in a I2C address of 0x47. The SDA and SCL must be pulled up to either 1.8 V or 3.3 V. When pulled up to 3.3 V, the VDD supply must be at least 3 V to keep from back-driving the I2C interface.

The TUSB320LA device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320LA device into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the EN_N pin is tied to GND. The TUSB320HA device can enter shutdown mode by pulling the EN pin low, which puts the TUSB320HA device into a low power state. In this case, external control of the EN pin is not implemented and therefore the EN pin is tied to 1.8 V or 3.3 V.

The INT_N/OUT3 pin is used to notify the PMIC when a change in the TUSB320 I2C registers occurs. This pin is an open drain output and requires an external pullup resistor. The pin should be pulled up to VDD using a 200-kΩ resistor.

The ID pin is used to indicate when a connection has occurred if the TUSB320 device is a DFP while configured for DRP. An OTG USB controller can use this pin to determine when to operate as a USB Host or USB Device. When this pin is driven low, the OTG USB controller functions as a host and then enables VBUS. The Type-C standard requires that a DFP not enable VBUS until the DFP is in the Attached.SRC state. If the ID pin is not low but VBUS is detected, then OTG USB controller functions as a device. The ID pin is open drain output and requires an external pullup resistor. THe ID pin should be pulled up to VDD using a 200-kΩ resistor.

The Type-C port mode is determined by the state of the PORT pin. When the PORT pin is not connected, the TUSB320 device is in DRP mode. The Type-C port mode can also be controlled by the MODE_SELECT register through the I2C interface.

The VBUS_DET pin must be connected through a 900-kΩ resistor to VBUS on the Type-C that is connected. This large resistor is required to protect the TUSB320 device from large VBUS voltage that is possible in present day systems. This resistor along with internal pulldown keeps the voltage observed by the TUSB320 device in the recommended range.

The USB2 specification requires the bulk capacitance on VBUS based on UFP or DFP. When operating the TUSB320 device in a DRP mode, it alternates between UFP and DFP. If the TUSB320 device connects as a UFP, the large bulk capacitance must be removed.

Table 14. USB2 Bulk Capacitance Requirements

PORT CONFIGURATION MIN MAX UNIT
Downstream facing port (DFP) 120 µF
Upstream facing port (UFP) 1 10 µF

8.2.1.3 Application Curves

TUSB320LAI TUSB320HAI DRP_appcurve_sllsen9_320.gif Figure 13. Application Curve for DRP in I2C Mode

8.2.2 DFP in I2C Mode

Figure 14 and Figure 15 show a Type-C configuration for the DFP mode.

TUSB320LAI TUSB320HAI app_typ_03_dfp_sllsen9_320.gif Figure 14. TUSB320 in DFP Mode Supporting Default Implementation
TUSB320LAI TUSB320HAI app_typ_06_dfp_sllsen9_320.gif Figure 15. TUSB320 in DFP Mode Supporting Advanced Power Delivery

Figure 16 shows the TUSB320 device configured as a DFP in I2C mode.

TUSB320LAI TUSB320HAI DFP_schematic_SLLSEQ8.gif Figure 16. DFP in I2C Mode Schematic

8.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 15:

Table 15. Design Requirements for DFP in I2C Mode

DESIGN PARAMETER VALUE
VDD (2.75 V to 5 V) 5 V
Mode (I2C or GPIO) I2C: ADDR pin must be pulled down or pulled up
I2C address (0x67 or 0x47) 0x47: ADDR pin must be pulled low or tied to GND
Type-C port type (UFP, DFP, or DRP) DFP: PORT pin is pulled up
Shutdown support No

8.2.2.2 Detailed Design Procedure

The TUSB320 device supports a VDD in the range of 2.75 V to 5 V. In this particular case, VDD is set to 5 V. A 100-nF capacitor is placed near VDD.

The TUSB320 device is placed into I2C mode by either pulling the ADDR pin high or low. In this particular case, the ADDR pin is tied to GND which results in a I2C address of 0x47. The SDA and SCL must be pulled up to either 1.8 V or 3.3 V. When pulled up to 3.3 V, the VDD supply must be at least 3 V to keep from back-driving the I2C interface.

The TUSB320LA device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320LA device into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the EN_N pin is tied to GND. The TUSB320HA device can enter shutdown mode by pulling the EN pin low, which puts the TUSB320HA device into a low power state. In this case, external control of the EN pin is not implemented and therefore the EN pin is tied to 1.8 V or 3.3 V.

The INT_N/OUT3 pin is used to notify the PMIC when a change in the TUSB320 I2C registers occurs. This pin is an open drain output and requires an external pullup resistor. The pin should be pulled up to VDD using a 200-kΩ resistor.

The Type-C port mode is determined by the state of the PORT pin. When the PORT pin is pulled high, the TUSB320 device is in DFP mode. The Type-C port mode can also be controlled by the MODE_SELECT register through the I2C interface.

The VBUS_DET pin must be connected through a 900-kΩ resistor to VBUS on the Type-C that is connected. This large resistor is required to protect the TUSB320 device from large VBUS voltage that is possible in present day systems. This resistor along with internal pulldown keeps the voltage observed by the TUSB320 device in the recommended range.

The USB2 specification requires the bulk capacitance on VBUS based on UFP or DFP. When operating the TUSB320 device in a DFP mode, a bulk capacitance of at least 120 µF is required. In this particular case, a 150-µF capacitor was chosen.

8.2.2.3 Application Curves

TUSB320LAI TUSB320HAI DFP_appcurve_sllsen9_320.gif Figure 17. Application Curve for DFP in I2C Mode

8.2.3 UFP in I2C Mode

Figure 18 and Figure 19 show a Type-C configuration for the UFP mode.

TUSB320LAI TUSB320HAI app_typ_02_ufp_sllsen9_320.gif Figure 18. TUSB320 in UFP Mode Supporting Default Implementation
TUSB320LAI TUSB320HAI app_typ_05_ufp_sllsen9_320.gif Figure 19. TUSB320 in UFP Mode Supporting Advanced Power Delivery

Figure 20 shows the TUSB320 device configured as a UFP in I2C mode.

TUSB320LAI TUSB320HAI UFP_schematic_SLLSEQ8.gif Figure 20. UFP in I2C Mode Schematic

8.2.3.1 Design Requirements

For this design example, use the parameters listed in Table 16:

Table 16. Design Requirements for UFP in I2C Mode

DESIGN PARAMETER VALUE
VDD (2.75 V to 5 V) 5 V
Mode (I2C or GPIO) I2C: ADDR pin must be pulled down or pulled up
I2C address (0x67 or 0x47) 0x47: ADDR pin must be pulled low or tied to GND
Type-C port type (UFP, DFP, or DRP) UFP: PORT pin is pulled down
Shutdown support No

8.2.3.2 Detailed Design Procedure

The TUSB320 device supports a VDD in the range of 2.75 V to 5 V. In this particular case, VDD is set to 5 V. A 100-nF capacitor is placed near VDD. If VBUS is guaranteed to be less than 5.5 V, powering the TUSB320 device through a diode can be implemented.

The TUSB320 device is placed into I2C mode by either pulling the ADDR pin high or low. In this case, the ADDR pin is tied to GND which results in a I2C address of 0x47. The SDA and SCL must be pulled up to either 1.8 V or 3.3 V. When pulled up to 3.3 V, the VDD supply must be at least 3 V to keep from back-driving the I2C interface.

The TUSB320LA device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320LA device into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the EN_N pin is tied to GND. The TUSB320HA device can enter shutdown mode by pulling the EN pin low, which puts the TUSB320HA device into a low power state. In this case, external control of the EN pin is not implemented and therefore the EN pin is tied to 1.8 V or 3.3 V.

The INT_N/OUT3 pin is used to notify the PMIC when a change in the TUSB320 I2C registers occurs. This pin is an open drain output and requires an external pullup resistor. The pin should be pulled up to VDD using a 200-kΩ resistor.

The Type-C port mode is determined by the state of the PORT pin. When the PORT pin is pulled low, the TUSB320 device is in UFP mode. The Type-C port mode can also be controlled by the MODE_SELECT register through the I2C interface.

The VBUS_DET pin must be connected through a 900-kΩ resistor to VBUS on the Type-C that is connected. This large resistor is required to protect the TUSB320 device from large VBUS voltage that is possible in present day systems. This resistor along with internal pulldown keeps the voltage observed by the TUSB320 device in the recommended range.

The USB2 specification requires the bulk capacitance on VBUS based on UFP or DFP. When operating the TUSB320 device in a UFP mode, a bulk capacitance between 1 µF to 10 µF is required. In this particular case, a 1-µF capacitor was chosen.

8.2.3.3 Application Curves

TUSB320LAI TUSB320HAI UFP_appcurve_sllsen9_320.gif Figure 21. Application Curve for UFP in I2C Mode

8.3 Initialization Setup

8.3.1 TUSB320LA Initialization Procedure

  1. System is powered off (device has no VDD). The TUSB320LA device is configured internally in UFP mode with Rds on CC pins (dead battery).
  2. VDD ramps – POR circuit. VDD must ramp within 25 ms or less. IO pull-up power rail (i.e. pull up on ID, INT, SCL, SDA, ADDR, PORT) must ramp with VDD or lag after VDD.
  3. I2C supply ramps up.
  4. The TUSB320LA device enters unattached mode and determines the voltage level from the PORT pin. This determines the mode in which the TUSB320LA device operates (DFP, UFP, DRP).
  5. The TUSB320LA device monitors the CC pins as a DFP and VBUS for attach as a UFP.
  6. The TUSB320LA device enters active mode when attach has been successfully detected.

8.3.2 TUSB320HA Initialization Procedure

  1. System is powered off (device has no VDD). The TUSB320HA device is configured internally in UFP mode with Rds on CC pins (dead battery).
  2. VDD ramps – POR circuit. VDD must ramp within 25 ms or less. IO pull-up power rail (i.e. pull up on ID, INT, SCL, SDA, ADDR, PORT) must ramp with VDD or lag after VDD.
  3. I2C supply ramps up.
  4. The TUSB320HA device enters unattached mode and determines the voltage level from the PORT pin. This determines the mode in which the TUSB320HA device operates (DFP, UFP, DRP).
  5. The TUSB320HA device monitors the CC pins as a DFP and VBUS for attach as a UFP.
  6. The TUSB320HA device enters active mode when attach has been successfully detected.