SLLSEI0D July   2015  – January 2022 TUSB4020BI

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Hub Input Supply Current
    7. 7.7 Power-Up Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 Clock Generation
      4. 8.3.4 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
    5. 8.5 Programming
      1. 8.5.1 One-Time Programmable (OTP) Configuration
      2. 8.5.2 I2C EEPROM Operation
      3. 8.5.3 SMBus Slave Operation
    6. 8.6 Register Maps
      1. 8.6.1 Configuration Registers
        1. 8.6.1.1  ROM Signature Register (offset = 0h) [reset = 0h]
        2. 8.6.1.2  Vendor ID LSB Register (offset = 1h) [reset = 51h]
        3. 8.6.1.3  Vendor ID MSB Register (offset = 2h) [reset = 4h]
        4. 8.6.1.4  Product ID LSB Register (offset = 3h) [reset = 25h]
        5. 8.6.1.5  Product ID MSB Register (offset = 4h) [reset = 80h]
        6. 8.6.1.6  Device Configuration Register (offset = 5h) [reset = 1Xh]
        7. 8.6.1.7  Battery Charging Support Register (offset = 6h) [reset = 0Xh]
        8. 8.6.1.8  Device Removable Configuration Register (offset = 7h) [reset = 0Xh]
        9. 8.6.1.9  Port Used Configuration Register (offset = 8h) [reset = 0h]
        10. 8.6.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]
        11. 8.6.1.11 Device Configuration Register 2 (offset = Ah)
        12. 8.6.1.12 UUID Registers (offset = 10h to 1Fh)
        13. 8.6.1.13 Language ID LSB Register (offset = 20h)
        14. 8.6.1.14 Language ID MSB Register (offset = 21h)
        15. 8.6.1.15 Serial Number String Length Register (offset = 22h)
        16. 8.6.1.16 Manufacturer String Length Register (offset = 23h)
        17. 8.6.1.17 Product String Length Register (offset = 24h)
        18. 8.6.1.18 Serial Number Registers (offset = 30h to 4Fh)
        19. 8.6.1.19 Manufacturer String Registers (offset = 50h to 8Fh)
        20. 8.6.1.20 Product String Registers (offset = 90h to CFh)
        21. 8.6.1.21 Additional Feature Configuration Register (offset = F0h)
        22. 8.6.1.22 Charging Port Control Register (offset = F2h)
        23. 8.6.1.23 Device Status and Command Register (offset = F8h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Crystal Requirements
      2. 9.1.2 Input Clock Requirements
    2. 9.2 Typical Applications
      1. 9.2.1 Upstream Port Implementation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Downstream Port 1 Implementation
      3. 9.2.3 Downstream Port 2 Implementation
      4. 9.2.4 VBUS Power Switch Implementation
      5. 9.2.5 Clock, Reset, and Miscellaneous
      6. 9.2.6 Power Implementation
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1.6 Device Configuration Register (offset = 5h) [reset = 1Xh]

Figure 8-7 Register Offset 5h
76543210
0001XX00
R/WR/WR/WRR/WR/WR/WR
LEGEND: R/W = Read/Write; R = Read only; –n = value after reset
Table 8-9 Device Configuration Register
BitFieldTypeResetDescription
7customStringsR/W1XhCustom strings enable. This bit controls the ability to write to the Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers.
0 = The Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers are read only.
1 = The Manufacturer String Length, Manufacturer String, Product String Length, Product String, and Language ID registers may be loaded by EEPROM or written by SMBus.
The default value of this bit is 0.
6customSernumR/W1XhCustom serial number enable. This bit controls the ability to write to the serial number registers.
0 = The Serial Number String Length and Serial Number String registers are read only.
1 = The Serial Number String Length and Serial Number String registers may be loaded by EEPROM or written by SMBus.
The default value of this bit is 0.
5RSVDR/W1XhReserved. This bit is reserved.
4RSVDR1XhReserved. This bit is reserved and returns 1 when read.
3gangedR/W1XhGanged. This bit is loaded at the deassertion of reset with the value of the GANGED/SMBA2/HS_UP terminal.
0 = When fullPwrMgmtz = 0, each port is individually power switched and enabled by the PWRCTL[2:1]/BATEN[2:1] terminals
1 = When fullPwrMgmtz = 0, the power switch control for all ports is ganged and enabled by the PWRCTL1/BATEN1 terminal
When the TUSB4020BI is in I2C mode, the TUSB4020BI loads this bit from the contents of the EEPROM.
When the TUSB4020BI is in SMBUS mode, the value may be overwritten by an SMBus host.
2fullPwrMgmtzR/W1XhFull Power Management. This bit is loaded at the deassertion of reset with the value of the FULLPWRMGMTz/SMBA1 terminal.
0 = Port power switching and over-current status reporting is enabled
1 = Port power switching and over-current status reporting is disabled
When the TUSB4020BI is in I2C mode, the TUSB4020BI loads this bit from the contents of the EEPROM.
When the TUSB4020BI is in SMBUS mode, the value may be overwritten by an SMBus host.
1RSVDR/W1XhReserved. This bit is reserved and should not be altered from the default.
0RSVDR1XhReserved. This field is reserved and returns 0 when read.