SLLSEF6C July   2014  – June 2017 TUSB8020B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One-Time Programmable (OTP) Configuration
      4. 8.3.4 Clock Generation
        1. 8.3.4.1 Crystal Requirements
        2. 8.3.4.2 Input Clock Requirements
      5. 8.3.5 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1 Configuration Registers
        1. 8.5.1.1  ROM Signature Register (offset = 0h) [reset = 0h]
        2. 8.5.1.2  Vendor ID LSB Register (offset = 1h) [reset = 51h]
        3. 8.5.1.3  Vendor ID MSB Register (offset = 2h) [reset = 4h]
        4. 8.5.1.4  Product ID LSB Register (offset = 3h) [reset = 25h]
        5. 8.5.1.5  Product ID MSB Register (offset = 4h) [reset = 80h]
        6. 8.5.1.6  Device Configuration Register (offset = 5h) [reset = 1Xh]
        7. 8.5.1.7  Battery Charging Support Register (offset = 6h) [reset = 0Xh]
        8. 8.5.1.8  Device Removable Configuration Register (offset = 7h) [reset = 0Xh]
        9. 8.5.1.9  Port Used Configuration Register (offset = 8h) [reset = 0h]
        10. 8.5.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]
        11. 8.5.1.11 Device Configuration Register 2 (offset = Ah)
        12. 8.5.1.12 UUID Registers (offset = 10h to 1Fh)
        13. 8.5.1.13 Language ID LSB Register (offset = 20h)
        14. 8.5.1.14 Language ID MSB Register (offset = 21h)
        15. 8.5.1.15 Serial Number String Length Register (offset = 22h)
        16. 8.5.1.16 Manufacturer String Length Register (offset = 23h)
        17. 8.5.1.17 Product String Length Register (offset = 24h)
        18. 8.5.1.18 Serial Number Registers (offset = 30h to 4Fh)
        19. 8.5.1.19 Manufacturer String Registers (offset = 50h to 8Fh)
        20. 8.5.1.20 Product String Registers (offset = 90h to CFh)
        21. 8.5.1.21 Additional Feature Configuration Register (offset = F0h)
        22. 8.5.1.22 Charging Port Control Register (offset = F2h)
        23. 8.5.1.23 Device Status and Command Register (offset = F8h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 VBUS Power Switch Implementation
        5. 9.2.2.5 Clock, Reset, and Miscellaneous
        6. 9.2.2.6 Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
      1. 11.2.1 Upstream Port
      2. 11.2.2 Downstream Port
      3. 11.2.3 Thermal Pad
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage Range VDD Steady-state supply voltage –0.3 1.4 V
VDD33 Steady-state supply voltage –0.3 3.8 V
Voltage Range USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1], USB_SSRXN_DP[4:1] and USB_VBUS terminals -0.3 1.4 V
XI terminals -0.3 2.45 V
All other terminals -0.3 3.8 V
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2000 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD(1) 1.1-V supply voltage 0.99 1.1 1.26 V
VDD33 3.3-V supply voltage 3 3.3 3.6 V
USB_VBUS Voltage at USB_VBUS PAD 0 1.155 V
TA Operating free-air temperature range TUSB8020B 0 25 70 °C
TUSB8020BI –40 25 85
TJ Operating junction temperature range –40 25 105 °C
(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

7.4 Thermal Information

THERMAL METRIC(1) TUSB8020B UNIT
PHP
48 PINS
RθJA Junction-to-ambient thermal resistance 31.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 16.1 °C/W
RθJB Junction-to-board thermal resistance 13 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 12.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 3.3-V I/O Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER OPERATION TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage(1) VDD33 2 VDD33 V
VIL Low-level input voltage(1) VDD33 0 0.8 V
VI Input voltage 0 VDD33 V
VO Output voltage(2) 0 VDD33 V
tt Input transition time (trise and tfall) 0 25 ns
Vhys Input hysteresis(3) 0.13 × VDD33 V
VOH High-level output voltage VDD33 IOH = –4 mA 2.4 V
VOL Low-level output voltage VDD33 IOL = 4 mA 0.4 V
IOZ High-impedance, output current(2) VDD33 VI = 0 to VDD33 ±20 µA
IOZP High-impedance, output current with internal pullup or pulldown resistor(4) VDD33 VI = 0 to VDD33 ±225 µA
II Input current(5) VDD33 VI = 0 to VDD33 ±15 µA
(1) Applies to external inputs and bidirectional buffers
(2) Applies to external outputs and bidirectional buffers
(3) Applies to GRSTz
(4) Applies to pins with internal pullups/pulldowns
(5) Applies to external input buffers

7.6 Power-Up Timing Requirements

MIN TYP MAX UNIT
td1 VDD33 stable before VDD stable. No timing relationship between VDD33 and VDD 0 ms
td2 VDD and VDD33 stable before deassertion of GRSTZ. 3 ms
tsu_io Setup for MISC inputs sampled at the deassertion of GRSTZ(1) 0.1 µs
thd_io Hold for MISC inputs sampled at the deassertion of GRSTZ.(1) 0.1 µs
tVDD33_RAMP VDD33 supply ramp requirements 0.2 100 ms
tVDD_RAMP VDD supply ramp requirements 0.2 100 ms
(1) Miscellaneous pins sampled at deassertion of GRSTZ: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN1, and BATEN2
TUSB8020B Pwr_up_timing_sllsef7.gif Figure 1. Power-Up Timing Requirements

7.7 Hub Input Supply Current

Typical values measured at TA = 25°C
PARAMETER VDD33 VDD11 UNIT
3.3 V 1.1 V
LOW-POWER MODES
Power-on (after reset)                    5 39 mA
Disconnect from host 5 39 mA
Suspend (USB2 host)                                   5 39 mA
Suspend (USB3 host) 6 40 mA
ACTIVE MODES (US STATE / DS STATE)
3.0 host / 1 SS device and hub in U1 50 218 mA
3.0 host / 1 SS device and hub in U0 50 342 mA
3.0 host / 2 SS devices and hub in U1 50 284 mA
3.0 host / 2 SS devices and hub in U0 50 456 mA
3.0 host / 1 SS and 1 HS device in U1 92 242 mA
3.0 host / 1 SS and 1 HS device in U0 93 364 mA
2.0 host / 1 HS device active 48 71 mA
2.0 host / 2 HS devices active 60 80 mA
SMBUS Programming current 79 225 mA