SLLSF94 June 2019 TUSB8043A
PRODUCTION DATA.
Bit No. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Description |
---|---|---|---|
7:2 | RSVD | RO | Reserved. Read only, returns 0 when read. |
1 | smbusRst | RSU | SMBus interface reset. This bit loads the registers back to their GRSTz values. Note, that since this bit can only be set when in SMBus mode the cfgActive bit is also reset to 1. When software sets this bit it must reconfigure the registers as necessary.
This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A write of 0 has no effect. |
0 | cfgActive | RCU | Configuration active. This bit indicates that configuration of the TUSB8043A is currently active. The bit is set by hardware when the device enters the I2C or SMBus mode. The TUSB8043A shall not connect on the upstream port while this bit is 1.
When in I2C mode, the bit is cleared by hardware when the TUSB8043A exits the I2C mode. When in the SMBus mode, this bit must be cleared by the SMBus host in order to exit the configuration mode and allow the upstream port to connect. The bit is cleared by a writing 1. A write of 0 has no effect. |