SLLSE67I March   2011  – March 2016 TUSB9261


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics for 3.3-V Digital I/O
    6. 6.6 SuperSpeed USB Power Consumption
    7. 6.7 High-Speed USB Power Consumption
    8. 6.8 Oscillator Specification
    9. 6.9 Crystal Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operation
        1. General Functionality
        2. Firmware Support
        3. GPIO/PWM LED Designations
        4. Power-Up and Reset Sequence
      2. 7.3.2 Clock Connections
        1. Clock Source Requirements
        2. Clock Source Selection Guide
    4. 7.4 Device Functional Modes
      1. 7.4.1 VBUS Power
      2. 7.4.2 External Power
      3. 7.4.3 External Voltage Regulator
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. PWM Terminals
        2. JTAG Interface
        3. Voltage Regulator Schematic
        4. SPI
  9. Power Supply Recommendations
    1. 9.1 Digital Supplies 1.1-V and 3.3-V
    2. 9.2 Analog Supplies 1.1-V and 3.3-V
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 High-Speed Differential Routing
      2. 10.1.2 SuperSpeed Differential Routing
      3. 10.1.3 SATA Differential Routing
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The device serves as a bridge between a downstream USB 3.0 host port and a SATA device such as a hard disk drive. A crystal or oscillator supplies the required clock source. A SPI flash device contains the firmware that is loaded into the TUSB9261 after the deassertion of RESET. Push buttons or any other desired logic can be connected to the TUSB9261 GPIO pins. The TUSB9261 can also output a pulse-width modulated signal that can be used to drive an activity LED.

8.2 Typical Application

TUSB9261 typ_sys_imp_lla315.gif Figure 2. Typical Application Schematic

8.2.1 Design Requirements

Table 2. Design Parameters

VDD supply 1.1 V
VDD33 supply 3.3 V
Upstream port USB support SS, HS, FS
Main supply VBUS
USB_VBUS resistor values 90.9 kΩ, 10 kΩ
Crystal frequency 40 MHz
SATA device SSD

8.2.2 Detailed Design Procedure PWM Terminals

The TUSB9261 has two pulse-width modulated output terminals.

Table 3 shows the default firmware configuration of PWMs.

Table 3. Default Firmware Configuration of PWMs

0 Primary Indicator LED:
ON when there is a USB connection. OFF when there is no connection.
Blinks during disk activity (Frequency: 5 Hz for USB2 or 10 Hz for USB3).
Fades when USB is in Suspend or U3 state.
1 Power indicator LED

PWM duty cycle will be 0% when the LED should be fully ON. JTAG Interface

The TUSB9261 supports JTAG for board-level test and debug support. Typically, these terminals are left unconnected or routed to a header to plug in an external JTAG controller. Table 4 shows the JTAG terminal names and internal resistor connection. The JTAG interface should be left unconnected if JTAG support is not required.

Table 4. Internal JTAG Resistor Termination

JTAG_TCK Pull down JTAG test clock
JTAG_TDI Pull up JTAG test data in
JTAG_TDO Pull down JTAG test data out
JTAG_TMS Pull up JTAG test mode select
JTAG_RSTZ Pull down JTAG reset Voltage Regulator Schematic

TUSB9261 sch_voltage_reg_llse67.gif SPI

A SPI system consists of one master device and one or more slave devices. The TUSB9261 is a SPI master providing the SPI clock, data-in, data-out, and up to three chip-select terminals.

The SPI has a 4-wire synchronous serial interface. Data communication is enabled with an active-low chip select terminal (SPI_CS[2:0]#). Data is transmitted with a 3-terminal interface consisting of terminals for serial data input (SPI_DATA_IN), serial data output (SPI_DATA_OUT) and serial clock (SPI_SCLK).

All SPI terminals have integrated pullup resistors. No external components are required to connect the SPI interface to an external SPI flash device. See Figure 3 for an example implementation of the SPI interface using one SPI slave device.

TUSB9261 spi_conn1_lla315.gif Figure 3. SPI Connection

The SPI_CLK is running at a fixed frequency of 18.75 MHz and its clocking mode is configured with a POLARITY of 0 and a PHASE of 1, this means that the SPI sends the data output one half-cycle before the first rising edges of SPI_CLK and on subsequent falling edges. Meanwhile, the input data is latched on the rising edge of SPI_CLK (see Figure 4 and Table 5 for a detailed timing description).

The flash memory is erased by the bootloader prior to programming and must use a word size of 8 bits with an address length of 24 bits and its program instruction must allow 256 bytes to be written in one operation. TI recommends a minimum flash size of 512 kb (64 k × 8). Table 5 shows SPI flash devices that have been tested with the TUSB9261.

TUSB9261 spi_characterization_lla315.gif Figure 4. SPI Characterization

Table 5. SPI Characterization Time

1 Cycle time SPICLK 53.3 ns
2 Positive SPI_CLK slope 2 ns
3 Negative SPI_CLK slope 3 ns
4 SPISCS – SPICLK edge(PHASE = 1) MIN: 53.3 ns
TYP: 80 ns
MAX: 93.3 ns
5 Output delay time, SPICLK TX edge to SPISIMO valid 260 ps
6 Output hold time, SPICLK RX edge to SPISIMO valid 26.7 ns
7 Setup time 22 ns
8 Hold time 500 ps
9 "SPICLK -SPISCS Phase = 1, Master" 13.3 ns