SLLSE67I March 2011 – March 2016 TUSB9261
The major functional blocks are as follows:
The TUSB9261 ROM contains boot code that executes after a global reset, which performs the initial configuration required to load a firmware image from an attached SPI flash memory to local RAM.
After the firmware is loaded, it configures the SATA advanced host controller interface host bus adapter (AHCI) and the USB device controller. In addition, the configuration of the AHCI includes a port reset, which initiates an out of band (OOB) TX sequence from the AHCI link layer to determine if a device is connected, and if so, negotiate the connection speed with the device (3.0 Gbps or 1.5 Gbps).
The configuration of the USB device controller includes creation of the descriptors, configuration of the device endpoints for support of UASP and USB mass storage class BOT, allocation of memory for the transmit request blocks (TRBs), and creation of the TRBs necessary to transmit and receive packet data over the USB. In addition, the firmware provides any other custom configuration required for application-specific implementation, for example, a HID interface for user initiated backup.
After the USB device controller configuration is complete, if a SATA device was detected during the AHCI configuration, the firmware connects the device to the USB bus when VBUS is detected. According to the USB 3.0 specification, the TUSB9261 initially tries to connect at SuperSpeed USB. If successful, it enters U0; otherwise, after the training time out, it enables the DP pullup and connects as a USB 2.0 high-speed or full-speed device depending on the speed supported by host or hub port.
When connected, the firmware presents the BOT interface as the primary interface and the UASP interface as the secondary interface. If the host stack is UASP aware, it can enable the UASP interface using a SET_INTERFACE request for alternate interface 1.
Following speed negotiation, the device should transmit a device to host (D2H) FIS with the device signature. This first D2H FIS is received by the link layer and copied to the port signature register. When firmware is notified of the device connection, it queries the device for capabilities using the IDENTIFY DEVICE command. Firmware then configures the device as appropriate for its interface and features supported, for example, an HDD that supports native command queuing (NCQ).
Default firmware support is provided for the following:
The default firmware provided by TI drives the GPIO and PWM outputs as listed in Table 1.
|GPIO0||Undefined. Can use HID commands to change to output low or high. [internal 100-µA PD]||Input|
|GPIO1||USB 3.0 Link State if U1/U2 enabled, otherwise [input with 100-µA PD]||Output|
|GPIO5||USB 3.0 Link State if U1/U2 enabled, otherwise [input with 100-µA PD]||Output|
|GPIO1/ GPIO5||USB3 power state (U0 to U3)||U0: Off/Off||Output|
|GPIO3||[INPUT with 100-µA PD] momentary push button||Input|
|GPIO4||Bus- or self-powered indicator. (GPIO level should be HIGH when self-powered). [internal 100-µA PD]||Input|
|GPIO6||Undefined. Can use HID commands to change to output low or high. [internal 100-µA PD]||Input|
|GPIO10||Undefined. Can use HID commands to change to output low or high. Compile option to configure as SATA drive power enable output. [internal 100-µA PU]||Input|
|GPIO11||Power fault indicator. [internal 100-µA PU]||Input|
|PWM0||Disk activity (LED blink rate is faster when connected at USB SuperSpeed), USB connection (LED on), and USB suspend (fading LED).||Output|
The LEDs on the TUSB9261 product development kit (PDK) board are connected as in Table 1. See the TUSB9261 PDK Guide for more information on GPIO LED connection and usage. This EVM is available for purchase. Contact TI for ordering information.
The core power (VDD) must be present and at its minimum high level prior to, or at the same time that, the I/O power (VDD33).
In addition, meet the following constraints:
A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when it is below that range, either stable or in transition.
A minimum reset duration of 2 ms is required. This is defined as the time when the power supplies are in the recommended operating range to the deassertion of GRSTz.
The TUSB9261 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead of a crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a crystal is used, the connection needs to follow these guidelines.
Because XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as possible and away from any switching leads. TI also recommends to minimize the capacitance between XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external capacitors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC should not be connected to PCB ground when using a crystal.
Load capacitance (Cload) of the crystal (varies with the crystal vendor) is the total capacitance value of the entire oscillation circuit system as seen from the crystal. It includes two external capacitors, CL1 and CL2, in Figure 1. The trace length between the decoupling capacitors and the corresponding power pins on the TUSB9261 must be minimized. TI also recommends that the trace length from the capacitor pad to the power or ground plane be minimized.
Reference clock jitter is an important parameter. Jitter on the reference clock degrades both the transmit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing system performance. Additionally, a particularly jittery reference clock may interfere with the PLL lock detection mechanism, forcing the lock detector to issue an Unlock signal. A good-quality, low-jitter reference clock is required to achieve compliance with supported USB3.0 standards. For example, USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random phase jitter calculated after applying jitter transfer function (JTF)). As the PLL typically has a number of additional jitter components, the reference clock jitter must be considerably below the overall jitter budget.
Power can be supplied by a USB cable on the terminal VBUS. When using power from VBUS, both the TUSB9261 and the SATA device are allowed to draw only up to 500 mA from VBUS when operating.
Power can be supplied from an external power source. When using an external power source, both the TUSB9261 and the SATA interface can draw all their current from the external supply.
Because the TUSB9261 requires two voltage supplies (1.1 V and 3.3 V), TI recommends a multi-channel voltage regulator. The TPS650061 or TPS65024x are good choices. The TPS650061 uses a DC-DC converter and two LDO regulators in a single package. The DC-DC converter can supply 1-A nominal current while the two LDOs can supply 300-mA nominal current. Because the 1.1-V supply can consume upwards of 340 mA of current, the DC-DC converter is ideal for supplying the 1.1-V current while the two LDOs can be used to supply 3.3-V current. Likewise the TPS65024x uses three DC-DC converters and three LDOs. Both devices also have a built-in supervisor circuit that can be connected to GRST on the TUSB9261.