SLLSE67I March   2011  – March 2016 TUSB9261

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics for 3.3-V Digital I/O
    6. 6.6 SuperSpeed USB Power Consumption
    7. 6.7 High-Speed USB Power Consumption
    8. 6.8 Oscillator Specification
    9. 6.9 Crystal Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operation
        1. 7.3.1.1 General Functionality
        2. 7.3.1.2 Firmware Support
        3. 7.3.1.3 GPIO/PWM LED Designations
        4. 7.3.1.4 Power-Up and Reset Sequence
      2. 7.3.2 Clock Connections
        1. 7.3.2.1 Clock Source Requirements
        2. 7.3.2.2 Clock Source Selection Guide
    4. 7.4 Device Functional Modes
      1. 7.4.1 VBUS Power
      2. 7.4.2 External Power
      3. 7.4.3 External Voltage Regulator
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 PWM Terminals
        2. 8.2.2.2 JTAG Interface
        3. 8.2.2.3 Voltage Regulator Schematic
        4. 8.2.2.4 SPI
  9. 9 Power Supply Recommendations
    1. 9.1 Digital Supplies 1.1-V and 3.3-V
    2. 9.2 Analog Supplies 1.1-V and 3.3-V
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 High-Speed Differential Routing
      2. 10.1.2 SuperSpeed Differential Routing
      3. 10.1.3 SATA Differential Routing
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PVP Package
48-Pin HTQFP
Top View
TUSB9261 po_lles67.gif

Signal Descriptions – I/O Definitions

I/O TYPE DESCRIPTION
I Input
O Output
I/O Input/output
PU Internal pullup resistor
PD Internal pulldown resistor
PWR Power signal

Clock and Reset Signals

PIN I/O DESCRIPTION
NAME NO.
GRSTz 4 I
PU		 Global power reset. This reset brings all of the TUSB9261 internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional.
XI 52 I Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal, a 1-MΩ feedback resistor is required between X1 and XO.
XO 54 O Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an external oscillator, this pin may be left unconnected. When using a crystal, a 1-MΩ feedback resistor is required between X1 and XO.
FREQSEL[1:0] 31, 30 I
PU		 Frequency select. These terminals indicate the oscillator input frequency and are used to configure the correct PLL multiplier. The field encoding is as follows:
FREQSEL[1] FREQSEL[0] INPUT CLOCK FREQUENCY
1 1 40 MHz

SATA Interface Signals(1)

PIN I/O DESCRIPTION
NAME NO.
SATA_TXP 57 O Serial ATA transmitter differential pair (positive)
SATA_TXM 56 O Serial ATA transmitter differential pair (negative)
SATA_RXP 60 I Serial ATA receiver differential pair (positive)
SATA_RXM 59 I Serial ATA receiver differential pair (negative)
(1) Note that the default firmware and reference design for the TUSB9261 have the SATA TXP/TXM swapped for ease of routing in the reference design. If you plan to use the TI default firmware please review the reference design in the TUSB9261 DEMO User’s Guide (SLLU139) for proper SATA connection.

USB Interface Signals

PIN I/O DESCRIPTION
NAME NO.
USB_SSTXP 43 O SuperSpeed USB transmitter differential pair (positive)
USB_SSTXM 42 O SuperSpeed USB transmitter differential pair (negative)
USB_SSRXP 46 I SuperSpeed USB receiver differential pair (positive)
USB_SSRXM 45 I SuperSpeed USB receiver differential pair (negative)
USB_DP 36 I/O USB high-speed differential transceiver (positive)
USB_DM 35 I/O USB high-speed differential transceiver (negative)
USB_VBUS 50 I USB bus power
USB_R1 38 O Precision resistor reference. A 10-kΩ ±1% resistor should be connected between R1 and R1RTN.
USB_R1RTN 39 I Precision resistor reference return

Serial Peripheral Interface (SPI) Signals

PIN I/O DESCRIPTION
NAME NO.
SPI_SCLK 17 O
PU		 SPI clock
SPI_DATA_OUT 18 O
PU		 SPI master data out
SPI_DATA_IN 20 I
PU		 SPI master data in
SPI_CS0 21 O
PU		 Primary SPI chip select for flash RAM
SPI_CS2/ 23 I/O
PU		 SPI chip select for additional peripherals. When not used for SPI chip select, this pin may be used as a general-purpose I/O.
GPIO11
SPI_CS1/ 22 I/O
PU		 SPI chip select for additional peripherals. When not used for SPI chip select, this pin may be used as a general-purpose I/O.
GPIO10

JTAG, GPIO, and PWM Signals

PIN I/O DESCRIPTION
NAME NO.
JTAG_TCK 25 I
PD		 JTAG test clock
JTAG_TDI 26 I
PU		 JTAG test data in
JTAG_TDO 27 O
PD		 JTAG test data out
JTAG_TMS 28 I
PU		 JTAG test mode select
JTAG_TRSTz 29 I
PD		 JTAG test reset
GPIO9/UART_TX 6 I/O
PU		 GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a UART channel. This pin defaults to a general-purpose output.
GPIO8/UART_RX 5 I/O
PU		 GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART channel. This pin defaults to a general-purpose output.
GPIO7 16 I/O
PD		 Configurable as general-purpose input/outputs
GPIO6 15 I/O
PD
GPIO5 14 I/O
PD
GPIO4 13 I/O
PD
GPIO3 11 I/O
PD
GPIO2 10 I/O
PD
GPIO1 9 I/O
PD
GPIO0 8 I/O
PD
PWM0 2 O
PD(1)		 Pulse-width modulation (PWM). Can be used to drive status LEDs.
PWM1 3 O
PD(1)
(1) PWM pulldown resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down resistors are enabled by default.

Power and Ground Signals

PIN I/O DESCRIPTION
NAME NO.
VDD 1 PWR 1.1-V power rail
12
19
32
33
41
47
49
55
61
63
VDD33 7 PWR 3.3-V power rail
24
51
VDDA33 34 PWR 3.3-V analog power rail
40
48
62
VSSOSC 53 PWR Oscillator ground. If using a crystal, this should not be connected to a PCB ground plane. If using an oscillator, this should be connected to PCB ground. See Clock Source Requirements for more details.
VSS 44 PWR Ground
58
VSS 65 PWR Ground – Thermal pad
NC 37 — No connect, leave floating
64