SLASE51A November   2014  – November 2014 TVB1440

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematics
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Equalization
      2. 8.3.2 Configurable Output
      3. 8.3.3 Squelch
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 Squelch Mode
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface
      2. 8.5.2 Receiver (IN[3:0]P/N) Adjustments
        1. 8.5.2.1 Equalization Level
        2. 8.5.2.2 Squelch Level
      3. 8.5.3 Main Link Output [OUT[3:0]P/N] Adjustments
        1. 8.5.3.1 LINK Address Space
      4. 8.5.4 Example Script
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 Common 4k2k TV Panel Configuration
          2. 9.1.1.2.2 1Max Stream Rate
          3. 9.1.1.2.3 Encoded Stream Rate
          4. 9.1.1.2.4 TVB1440 Configuration
          5. 9.1.1.2.5 Receiver Equalization Setting
          6. 9.1.1.2.6 Transmitter Settings
          7. 9.1.1.2.7 RESET
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequence
    2. 10.2 Power-Down Sequence
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Differential Pairs
      2. 11.1.2 Layout Example
      3. 11.1.3 Placement
      4. 11.1.4 Package Specific
      5. 11.1.5 Ground
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Export Control Notice
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

TVB1440 is a 4 channel HS re-driver signal conditioner for TV applications. I2C control provides the wide ranges of flexibility to configure the device for optimal signal conditioning so that video data link between a source and sink can achieve high fidelity. TVB1440 allows larger distance between a Chipset and TCON boards through its excellent jitter cleaning capability.

The TVB1440 is optimized for power conscience applications. Apart from its low active power, TVB1440 contains activity detection circuitry on the data link input that transitions to a low-power output disable mode in the absence of a valid input signal. This activity detect circuit can be disabled if desired. The device also has a shutdown mode when exercised results in 2 mW.

The TVB1440 receiver and driver provide input and output common mode voltage bias. It is required that both receive and transmit end of the device is ac coupled in application use cases. Suggested value for the ac coupling capacitors is 75-200 nF.

8.2 Functional Block Diagram

fbd_slase51.gif

8.3 Feature Description

8.3.1 Equalization

TVB1440 provides flexible continuous time linear equalization (CTLE) to compensate for large trace or cable loss at its input resulting improved eye at the output signals. It has selectable control for receive equalization accessible through I2C.

8.3.2 Configurable Output

Transmitter in each channel has 4 levels of pre-emphasis and 4 levels of output voltage swing settings which enable optimum video signal performance from the TVB1440 to downstream receiver.

8.3.3 Squelch

TVB1440 has active Squelch feature that allows automatic shutdown of output drivers when it does not have valid input signal. The feature can be disabled through I2C if not desired.

8.4 Device Functional Modes

8.4.1 Active Mode

Normal operation mode. The data lanes of TVB1440 work normally.

8.4.2 Shutdown Mode

Device is in lowest power mode. This mode is invoked by de-asserting RSTN or EN low.

8.4.3 Squelch Mode

The device does not have valid input signal. Output drivers are turned off.

8.5 Programming

8.5.1 Local I2C Interface

It is required to use the TVB1440’s local I2C interface to configure the TVB1440’s receivers (IN[3:0]P/N) and transmitters (OUT[3:0]P/N). The TVB1440’s internal registers are accessed through the SCL_CTL pin and SDA_CTL pin. The 7-bit I2C slave address of the TVB1440 is determined by the ADDR pin.

Table 1. TVB1440 I2C Slave Address Options

ADDR 7-BIT I2C SLAVE ADDRESS READ SLAVE ADDRESS WRITE SLAVE ADDRESS
Low (VIL) 7’b0101100 ‘h59 ‘h58
VCC/2 (VIM) 7’b0101101 ‘h5B ‘h5A
High (VIH) 7’b0101110 ‘h5D ‘h5C

Before adjusting the TVB1440’s registers, a writing a zero to bit 2 of address 04h is required to enable the receiver and transmitter adjustments.

8.5.2 Receiver (IN[3:0]P/N) Adjustments

8.5.2.1 Equalization Level

It is recommended to use the TVB1440 local I2C interface to configure the TVB1440 receiver equalization level. Software should then enable equalization control by writing a one to EQ_I2C_ENABLE bit (bit 7 at address 05h). After EQ_I2C_ENABLE is set, then software can program the equalization for each lane (IN[3:0]) to the appropriate value. Refer to Table 2 for details on equalization settings for each lane.

Table 2. TVB1440 Equalization Levels

Address Bits(s) Description Access
04h 2 Receiver and transmitter adjustment.
0 – configure receiver and transmitter using I2C (required)
1 – reserved (default)		 RW
05h 2:0 EQ_LEVEL_LANE0. This field selects the EQ gain level for Lane 0 (IN0P/N).
000 – 0 dB
001 – 2 dB (3.75Gbps); 2.5 dB (5Gbps)
010 – 3.5 dB (3.75Gbps); 5 dB (5Gbps)
011 – 5 dB (3.75Gbps); 6 dB (5Gbps)
100 – 6.5 dB (3.75Gbps); 8 dB (5Gbps)
101 – 8 dB (3.75Gbps); 11 dB (5Gbps)
110 – 9.5 dB (3.75Gbps); 13 dB (5Gbps)
111 – 12 dB (3.75Gbps); 15 dB (5Gbps)		 RW
05h 7 EQ_I2C_ENABLE. This field allows EQ control through I2C
0 – reserved (default)
1 – EQ level is set by I2C (required)		 RW
07h 2:0 EQ_LEVEL_LANE1. This field selects the EQ gain level for Lane 1 (IN1P/N. Bit definition identical to that of EQ_LEVEL_LANE0. RW
09h 2:0 EQ_LEVEL_LANE2. This field selects the EQ gain level for Lane 2 (IN2P/N). Bit definition identical to that of EQ_LEVEL_LANE0. RW
0Bh 2:0 EQ_LEVEL_LANE3. This field selects the EQ gain level for Lane 3 (IN3P/N. Bit definition identical to that of EQ_LEVEL_LANE0. RW

8.5.2.2 Squelch Level

The TVB1440 squelch level defaults to 80mVpp. If it is necessary to adjust the squelch level, it can be done by changing the SQUELCH_SENSITIVITY register located in the TVB1440’s Local I2C register space.

Table 3. Squelch Sensitivity Levels

Address Bits(s) Description Access
03h 5:4 SQUELCH_SENSITIVITY. Main link squelch sensitivity is selected by this field, and determines the transitions to and from the Output Disable mode.
00 – Main Link IN0P/N squelch detection threshold is set to 40mVpp.
01 – Main Link IN0P/N squelch detection threshold is set to 80mVpp. (Default)
10 – Main Link IN0P/N squelch detection threshold is set to 160mVpp.
11 – Main Link IN0P/N squelch detection threshold is set to 250mVpp.		 RW
3 SQUELCH_ENABLE.
0 – Main Link IN0P/N squelch detection is enabled (default)
1 – Main Link IN0P/N squelch detection is disabled.		 RW

8.5.3 Main Link Output [OUT[3:0]P/N] Adjustments

The TVB1440 Main link outputs (OUT[3:0]) must be set in link address space by following specified I2C access method.

8.5.3.1 LINK Address Space

Access to and from the TVB1440 LINK address space is indirectly addressable through the local I2C registers as illustrated in the Figure 8.

link_registers_slase51.gifFigure 8. Accessing TVB1440 LINK Registers

The configuration of these registers can be performed through the local I2C interface, where three registers (from 1Ch to 1Eh) are used as the address to the LINK register and another one (1Fh) as a data to be read/written.

8.5.4 Example Script

The script below is for a Total Phase Aardvark I2C controller. Details on the Total Phase Aardvark I2C controller can be obtained from the Total Phase website. This example is for a 5.0 Gbps data rate with 4 active lanes.

<aardvark> <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="0"/> <i2c_bitrate khz="100"/> ======Program the device===== <i2c_write addr="0x2D" count="1" radix="16">04 00</i2c_write> /> ======Program Link Bandwidth Settings to 5Gbps======LINK 00100h===== <i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1E 00</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1F 14</i2c_write> /> ======Program Num of Lanes to 4.s======LINK 00101h===== <i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1E 01</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1F 04</i2c_write> /> ======Program VOD L1 and Pre-Emphasis L0 for Lane 0======LINK 00103h===== <i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1E 03</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> /> ======Program VOD L1 and Pre-Emphasis L0 for Lane 1======LINK 00104h===== <i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1E 04</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> /> ======Program VOD L1 and Pre-Emphasis L0 for Lane 2======LINK 00105h===== <i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1E 05</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> /> ======Program VOD L1 and Pre-Emphasis L0 for Lane 3======LINK 00106h===== <i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1D 01</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1E 06</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> /> ======Set Power Mode to Normal======LINK 00600h===== <i2c_write addr="0x2D" count="1" radix="16">1C 00</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1D 06</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1E 00</i2c_write> /> <i2c_write addr="0x2D" count="1" radix="16">1F 01</i2c_write> /> =====May want to adjust Squelch Level=== <i2c_write addr="0x2D" count="1" radix="16">03 10</i2c_write> /> =====Enable EQ=== <i2c_write addr="0x2D" count="1" radix="16">05 80</i2c_write> /> =====Set EQ level to 11dB(5Gbps) for lane 0=== <i2c_write addr="0x2D" count="1" radix="16">05 85</i2c_write> /> =====Set EQ level to 11dB(5Gbps) for lane 1=== <i2c_write addr="0x2D" count="1" radix="16">07 05</i2c_write> /> =====Set EQ level to 11dB(5Gbps) for lane 2=== <i2c_write addr="0x2D" count="1" radix="16">09 05</i2c_write> /> =====Set EQ level to 11dB(5Gbps) for lane 3=== <i2c_write addr="0x2D" count="1" radix="16">0B 05</i2c_write> /> </aardvark>

8.6 Register Maps

Table 4. TVB1440 LINK Registers

LINK Address NAME Value Written Value Read Description
00100h LINK_BW_SET 06h 00h <1.6Gbps per lane
0Ah 01h 1.6-2.7Gbps per lane
14h 02h 2.7-5.0Gbps per lane
00101h LANE_COUNT_SET 00h 00h All Lanes disabled
01h 01h One lane enabled (OUT0).
02h 03h Two lanes enabled (OUT[1:0]).
04h 0Fh Four lanes enabled (OUT[3:0]).
00103h LANE0_SET 00h 00h VOD Level 0 and Pre-emphasis Level 0 for OUT0.
08h 04h VOD Level 0 and Pre-emphasis Level 1 for OUT0.
10h 08h VOD Level 0 and Pre-emphasis Level 2 for OUT0.
18h 0Ch VOD Level 0 and Pre-emphasis Level 3 for OUT0.
01h 01h VOD Level 1 and Pre-emphasis Level 0 for OUT0.
09h 05h VOD Level 1 and Pre-emphasis Level 1 for OUT0.
11h 09h VOD Level 1 and Pre-emphasis Level 2 for OUT0.
02h 02h VOD Level 2 and Pre-emphasis Level 0 for OUT0.
0Ah 06h VOD Level 2 and Pre-emphasis Level 1 for OUT0.
03h 03h VOD Level 3 and Pre-emphasis Level 0 for OUT0
00104h LANE1_SET 00h 00h VOD Level 0 and Pre-emphasis Level 0 for OUT1.
08h 04h VOD Level 0 and Pre-emphasis Level 1 for OUT1.
10h 08h VOD Level 0 and Pre-emphasis Level 2 for OUT1.
18h 0Ch VOD Level 0 and Pre-emphasis Level 3 for OUT1.
01h 01h VOD Level 1 and Pre-emphasis Level 0 for OUT1.
09h 05h VOD Level 1 and Pre-emphasis Level 1 for OUT1.
11h 09h VOD Level 1 and Pre-emphasis Level 2 for OUT1.
02h 02h VOD Level 2 and Pre-emphasis Level 0 for OUT1.
0Ah 06h VOD Level 2 and Pre-emphasis Level 1 for OUT1.
03h 03h VOD Level 3 and Pre-emphasis Level 0 for OUT1
00105h LANE2_SET 00h 00h VOD Level 0 and Pre-emphasis Level 0 for OUT2.
08h 04h VOD Level 0 and Pre-emphasis Level 1 for OUT2.
10h 08h VOD Level 0 and Pre-emphasis Level 2 for OUT2.
18h 0Ch VOD Level 0 and Pre-emphasis Level 3 for OUT2.
01h 01h VOD Level 1 and Pre-emphasis Level 0 for OUT2.
09h 05h VOD Level 1 and Pre-emphasis Level 1 for OUT2.
11h 09h VOD Level 1 and Pre-emphasis Level 2 for OUT2.
02h 02h VOD Level 2 and Pre-emphasis Level 0 for OUT2.
0Ah 06h VOD Level 2 and Pre-emphasis Level 1 for OUT2.
03h 03h VOD Level 3 and Pre-emphasis Level 0 for OUT2
00106h LANE3_SET 00h 00h VOD Level 0 and Pre-emphasis Level 0 for OUT3.
08h 04h VOD Level 0 and Pre-emphasis Level 1 for OUT3.
10h 08h VOD Level 0 and Pre-emphasis Level 2 for OUT3.
18h 0Ch VOD Level 0 and Pre-emphasis Level 3 for OUT3.
01h 01h VOD Level 1 and Pre-emphasis Level 0 for OUT3.
09h 05h VOD Level 1 and Pre-emphasis Level 1 for OUT3.
11h 09h VOD Level 1 and Pre-emphasis Level 2 for OUT3.
02h 02h VOD Level 2 and Pre-emphasis Level 0 for OUT3.
0Ah 06h VOD Level 2 and Pre-emphasis Level 1 for OUT3.
03h 03h VOD Level 3 and Pre-emphasis Level 0 for OUT3
00600h SET_POWER 01h 00h Normal Mode
02h 01h Power-Down mode.