SCES990 May   2025

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Supply Current
    7. 5.7  Switching Characteristics, VCCA = 1.8 ± 0.15V
    8. 5.8  Switching Characteristics, VCCA = 2.5 ± 0.2V
    9. 5.9  Switching Characteristics, VCCA = 3.3 ± 0.3V
    10. 5.10 Switching Characteristics, VCCA = 5.0 ± 0.5V
    11. 5.11 Switching Characteristics: Tsk, TMAX
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 7.3.1.1 Inputs with Integrated Static Pull-Down Resistors
      2. 7.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 7.3.3 VCC Disconnect
      4. 7.3.4 Over-Voltage Tolerant Inputs
      5. 7.3.5 Glitch-Free Power Supply Sequencing
      6. 7.3.6 Negative Clamping Diodes
      7. 7.3.7 Fully Configurable Dual-Rail Design
      8. 7.3.8 Supports High-Speed Translation
      9. 7.3.9 AC Noise Rejection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Regulatory Requirements
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TXG804x-Q1 is a 4-bit ground-level translator that uses two individually configurable power-supply rails which allows it to translate across two different power domains. The device is operational with VCCA and VCCB supplies as low as 1.71V and as high as 5.5V. The A port is designed to track VCCA and the B port is designed to track VCCB. In addition to I/O level shifting, this translator can support a difference of -80V to +80V between GNDA and GNDB. VCCA is referenced to GNDA and VCCB is referenced to GNDB.

The TXG804x-Q1 device is designed for asynchronous communication between data buses, and transmits data with fixed direction from the A bus to the B bus on some channels and from the B bus to the A bus on the remaining channels. The output-enable input (OE) is used to disable the outputs so the buses are effectively isolated. The OE_A pin is referenced to VCCA and OE_B pin is referenced to VCCB. The OE pin can be left floating or externally pulled down to ground to keep the translator outputs in a high-impedance state during power-up or power-down.

The VCC disconnect feature ensures that if VCC is disconnected with the complementary supply within recommended operating conditions, outputs are disabled and set to the high-impedance state while the supply current is maintained. The Ioff-float circuitry ensures that no excessive current is drawn from or sourced into an input or output while the supply is floating.

Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance.