SLUS224G September   1994  – July 2022 UC1842A , UC1843A , UC1844A , UC1845A , UC2842A , UC2843A , UC2844A , UC2845A , UC3842A , UC3843A , UC3844A , UC3845A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse-by-Pulse Current Limiting
      2. 7.3.2 Current Sense Circuit
      3. 7.3.3 Error Amplifier Configuration
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Undervoltage Lockout (UVLO) Start-Up
      3. 7.4.3 UVLO Turnoff Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 UC2842A Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 CDIP, PDIP, and SOIC Packages, 8-Pin JG, P, and D (Top View)
Figure 5-3 SOIC Package, 14-Pin D (Top View)
Figure 5-2 LCCC and PLCC Packages, 20-Pin FK and FN (Top View)
Figure 5-4 SOIC Package, 16-Pin DW (Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
CDIP (8), PDIP (8), SOIC (8) LCCC (20), PLCC (20) SOIC (14) SOIC (16)
COMP 1 2 1 3 O Outputs the low impedance 1-MHz internal error amplifier that is also the input to the peak current limit or PWM comparator, with an open-loop gain (AVOL) of 80 dB. This pin is capable of sinking a maximum of 6 mA and is not internally current limited.
FB 2 5 3 4 I Input to the error amplifier that can be used to control the power converter voltage-feedback loop for stability.
GND 5 13 9 11 — This is the controller signal ground.
ISENSE 3 7 5 5 I Input to the peak current limit, PWM comparator of the UCx84xA controllers. When used in conjunction with a current sense resistor, the error amplifier output voltage controls the power systems cycle-by-cycle peak current limit. The maximum peak current sense signal is internally clamped to 1 V. See Section 7.2.
OUTPUT 6 15 10 12 O Output of 1-A totem pole gate driver. This pin can sink and source up to 1 A of gate driver current. A gate driver resistor must be used to limit the gate driver current.
PGND — 12 8 10 — Power ground and the gate driver return. For devices that have this pin, star grounding techniques can be used to redirect the gate driver current away from the signal ground pin (GND). This technique can reduce PWM controller instabilities caused by gate driver return current.
RT/CT 4 10 7 6 I Input to the internal oscillator that is programmed with an external timing resistor (RT) and timing capacitor (CT). See Section 7.3.5 for information on properly selecting these timing components. TI recommends using capacitance values from 470 pF to 4.7 nF. TI also recommends that the timing resistor values chosen be from 5 kΩ to 100 kΩ.
VC — 17 11 — I Bias input to the gate driver. For PWM controllers that do not have this pin, the gate driver is biased from the VCC pin. This pin must have a biasing capacitor that is at least 10 times greater than the gate capacitance of the main switching FET used in the design.
VCC 7 18 12 13, 14 I Bias input to the gate driver. This pin must have a biasing capacitor that is at least 10 times greater than the gate capacitance of the main switching FET used in the design.
VREF 8 20 14 15 O Reference voltage output of the PWM controller. This pin must supply no more than 10 mA under normal operation. This output is short-circuit protected at roughly 100 mA. This reference is also used for internal comparators and needs a high frequency bypass capacitor of 1 µF. The VCC capacitor also must be at least 10 times greater than the capacitor on the VREF pin.
NC — 1, 3, 4, 6, 8, 9, 11, 14, 16, 19 2, 4, 6, 13 1, 2, 7, 8, 9, 16 — No connection